industry news
Subscribe Now

DVCon U.S. 2024 Announces Keynote Speakers & Panel Focused on Generative AI

Gainesville, FL – February 15, 2024 – The 2024 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announced today that there will be two keynote speakers for attendees this year as well as a panel focused on generative Artificial Intelligence (AI). DVCon U.S. 2024 will be held March 4-7 at the DoubleTree by Hilton Hotel in San Jose, California.

The first keynote, “Addressing the Evolving Landscape of Automotive SoCs,” will be held on Tuesday, March 5 at 1:30 pm. It will be presented by Paul Cunningham, senior vice president and general manager of the system & verification group of Cadence Design Systems and his guest, Anthony Hill, a Texas Instruments (TI) Fellow, who also leads the Technology Backplane Organization for TI’s Processors Business.

Alex Starr, AMD Corporate Fellow responsible for AMD’s Shift Left Initiative and Verification Strategy, will present the second keynote, “From Chips to Checkered Flags: The Race Towards Real World Innovation,” on Wednesday, March 6 at 1:30 pm.

Wednesday, March 6, will begin at 8:00 am with a thought-provoking panel, “When Will We Be Able to Say, ‘EDA-GPT, Verify My ASIC?’” This panel invites participants to share and discuss their perspectives, experiences, insights, and apprehensions regarding the role of generative AI in verification. The panel will be moderated by Harry Foster, Chief Scientist Verification, Siemens EDA. Panelists include Daniel Schostak, Verification Architect & Fellow, ARM; Dan Yu, AI/ML Solutions Manager, Siemens EDA; Erik Berg, Principal SoC Verification Engineer, Microsoft; and Mark Ren, Director of Design and Automation Research, NVIDIA.

Other conference highlights include:

  • Accellera-sponsored luncheon on March 4 will focus on the Federated Simulation Standard Proposed Working Group (FSS PWG). Mark Burton, the FSS PWG Vice Chair will present the intent of the PWG. He will be joined by Yury Bayda, Principal Software Engineer at Ford Motor Company, who will discuss how a Federated Simulation standard will be beneficial to Ford.
  • Poster Ninja Warrior session on Wednesday, March 4 will include the top four posters battling it out for the Best Poster Award. Posters will be judged on a variety of factors, including audience reaction.

Registration for the keynotes, panel and exhibits-only is free. For more information and to register, visit the registration page.

For more information on the complete program, including the latest updates regarding the conference and expo, please visit the website.

About DVCon

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit For more information about DVCon U.S., please visit here. Follow DVCon on FacebookLinkedIn or @dvcon_us on Twitter or to comment, please use #dvcon_us.

Leave a Reply

featured blogs
Apr 19, 2024
In today's rapidly evolving digital landscape, staying at the cutting edge is crucial to success. For MaxLinear, bridging the gap between firmware and hardware development has been pivotal. All of the company's products solve critical communication and high-frequency analysis...
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...
Apr 18, 2024
See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.The post Cisco Accelerates Project Schedule by 66% Using Synopsys Cloud appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Audio Design for Augmented and Virtual Reality (AR/VR) Glasses
Open ear audio can be beneficial to a host of different applications including virtual reality headsets, smart glasses, and sports and fitness designs. In this episode of Chalk Talk, Amelia Dalton and Ryan Boyle from Analog Devices explore the what, where, and how of open ear audio. We also investigate the solutions that Analog Devices has for open ear audio applications and how you can design open ear audio into your next application. 
Jan 23, 2024