editor's blog archive
Subscribe to EE Journal Daily Newsletter
7 + 2 =

Write Once, Read Many

When a foundry prepares a process for a designer to use, it’s got to communicate how that process works and how it can be used. Which has to be couched in terms that an EDA tool can use.

Problem is, each foundry has its parameters and such, and each EDA tool has its formats and such. The same information ends up getting done and redone and redone in order to cover all the players.

There have been efforts to corral this to some extent by TSMC (at the very least) with their ixxx ( … Read More → "Write Once, Read Many"

Xtreme Update

We recently looked at a novel approach used by Xtreme to generate enough photons for EUV lithography. Just last week, there was a meeting of EUV folks to update their latest results.  I talked with Olivier Semprez about what Xtreme reported.

The goal here is to provide enough power to process 60 wafers/hr. That comes to 100 W with at least a 60% duty cycle.

The duty cycle issue comes from the logistics of exposing wafers. … Read More → "Xtreme Update"

Sensors for Medical and Fitness

While Movea’s main announcement recently was focused on their MoveTV product, they’ve actually been working with so-called body-area networks for a long time. This involves the placement of sensors on various parts of the human body, to be used for different purposes. While one use is for motion animation, there are also medical and fitness-related applications.

In particular, it has found use in physical therapy, where the sensors can monitor progress and pinpoint issues.

Moving further into the sports and fitness … Read More → "Sensors for Medical and Fitness"

MEMS over Copper

You may recall that there are various ways to approach CMOS-compatible MEMS. The one that yields the smallest die area is the CMOS-first process, where the CMOS circuits are built and then the MEMS layers are added afterwards. Done properly, it means the MEMS portions can be built right on top of the circuitry – this is, of course, what provides the space savings.

Imec has been doing a lot of work in this space, and in our earlier article, we pointed to their preference for poly-SiGe … Read More → "MEMS over Copper"

Abrasive-Free CMP

When it comes to the kinds of integration we see today, it’s hard to find something more important than chemical/mechanical planarization (CMP) as an enabling technology. Before that, we could only use a couple layers of metal, and after that, the surface just got too irregular to support additional reliable layers. Given the ability to smooth it all out, we seem to be able to go layer after layer without stopping.

The whole chemical/mechanical thing suggests scrubbing with abrasives, along with some chemical etching to encourage things along. Which is more or less … Read More → "Abrasive-Free CMP"

Serial Protocol Chameleon

We recently looked at Tektronix’s strategy for their new Veridae acquisition, but we also looked more broadly at their overall focuses, one of which is on serial links. They recently demonstrated a platform for testing such links.

There’s been a tendency for test boxes to be confined to individual protocols or families of protocols; their main point here is the integration of numerous protocols in the one box. Specifically, they list as examples Ethernet, Fibre Channel, Common Public Radio Interface ( … Read More → "Serial Protocol Chameleon"

Bridging Digital and Custom Domains

Digital and custom (mostly meaning analog) design domains have remained stubbornly separate for a long time. It used to make sense: digital flows were used for logic chips; custom flows were used either for hand-crafted processors, for highly-repetitive circuits like FPGAs and memories, or for analog chips. You designed an entire chip with one flow, so the fact that there were two domains didn’t matter.

The difference in flows more or less comes down to one word: synthesis. Logic can be synthesized and auto-placed and routed; custom circuits can’t. Or, by design, aren& … Read More → "Bridging Digital and Custom Domains"

EDA is sitting nervously on the

EDA is sitting nervously on the side of the pool, dipping one toe in, pulling it back out quickly. The cloud is out there, calling… EDA is both intrigued and afraid.

More than just about any segment of the software industry, EDA has struggled through the years to find the right business model – one that would let them make reliable, predictable profits – earning a return on their development and marketing investment, and serving their customers well. We’ve seen a variety of attempts including perpetual licensing plus maintenance/support fees, term licensing, and complicated all-you-can-eat or remix … Read More → "EDA is sitting nervously on the"

featured blogs
Nov 17, 2017
CASPA is the Chinese American Semiconductor Professional Association. Once a year they have their annual conference and dinner banquet. I ended up getting involved with them a few years ago when I stepped in with 24-hours' notice to moderate a panel session for them, plu...
Nov 15, 2017
SuperComputing 2017 remains in full force this week from the Colorado Convention Center in Denver.  There are lots of activity in presentations, seminars, demonstrations and exhibits on the tradeshow floor. Stay tuned to the Samtec blog the rest of the week for more highligh...
Nov 16, 2017
“Mommy, Daddy … Why is the sky blue?” As you scramble for an answer that lies somewhere between a discussion of refraction in gasses and “Oh, look—a doggie!” you already know the response to whatever you say will be a horrifyingly sincere “B...
Nov 07, 2017
Given that the industry is beginning to reach the limits of what can physically and economically be achieved through further shrinkage of process geometries, reducing feature size and increasing transistor counts is no longer achieving the same result it once did. Instead the...