editor's blog
Subscribe Now

Bridging Digital and Custom Domains

Digital and custom (mostly meaning analog) design domains have remained stubbornly separate for a long time. It used to make sense: digital flows were used for logic chips; custom flows were used either for hand-crafted processors, for highly-repetitive circuits like FPGAs and memories, or for analog chips. You designed an entire chip with one flow, so the fact that there were two domains didn’t matter.

The difference in flows more or less comes down to one word: synthesis. Logic can be synthesized and auto-placed and routed; custom circuits can’t. Or, by design, aren’t.

But chips aren’t so neatly segregated now. Analog chips now need digital control. Large SoC chips need analog content. But the two flows don’t really work together well. You end up having to do two partial designs and then go back and forth importing and exporting data. Problem is, in addition to the basic design data, there is lots of metadata: constraints and manual edits to placement and routing. These tend to get lost in the transfer.

So Synopsys recently announced an improvement to this process. It provides for a seamless, lossless transfer of information back and forth between domains. That ensures that all the metadata is included in the import/exports.

What it doesn’t do is combine the domains into one. Synopsys says that the two design styles are different enough to warrant different optimized databases. (Something tells me that, given demand, it would be possible to design an optimized combined database schema, although it might be a lot of work to create and migrate…)

But here’s what I think the real issue is: the digital side is on a proprietary database – useful for keeping customers in the Synopsys camp. The custom side is in an open database: useful for peeling away Cadence users. It will probably take more than ease-of-use to trump those strategic goals…

More info in their press release

Leave a Reply

featured blogs
Sep 21, 2020
Technology is changing the strategies we use to do things - oh so fast that 2010 seems like a distant past- within many spaces -- including the way we do our current topic of interest - Timing... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Sep 21, 2020
Semicon, the world’s largest semiconductor conference and exhibition, is September 23-25 in Taiwan. Like most shows of its size and caliber, Semicon boasts a long and illustrious list of exhibitors (500+), and countless forums, symposiums, and workshops. Of course Semic...
Sep 18, 2020
[From the last episode: We put the various pieces of a memory together to show the whole thing.] Before we finally turn our memory discussion into an AI discussion, let'€™s take on one annoying little detail that I'€™ve referred to a few times, but have kept putting off. ...
Sep 16, 2020
In addition to the Great Highland (Scottish) bagpipes, the Uilleann (Irish) bagpipes, and the Northumbrian (English) bagpipes, there are myriad other offerings spanning the globe....

Featured Video

Product Update: Family of DesignWare Ethernet IP for Time-Sensitive Networking

Sponsored by Synopsys

Hear John Swanson, our product expert, give an update on Synopsys’ DesignWare® Ethernet IP for Time-Sensitive Networking (TSN), which is compliant with IEEE standards and enables predictable guaranteed latency in automotive ADAS and industrial automation SoCs.

Click here for more information about DesignWare Ethernet Quality-of-Service Controller IP

Featured Paper

An Introduction to Automotive LIDAR

Sponsored by Texas Instruments

This white paper is an introduction to industrial and automotive time-of-flight (ToF) light detection and ranging (LIDAR) solutions to serve next-generation autonomous systems.

Click here to download the whitepaper

Featured Chalk Talk

Cadence Celsius Thermal Solver

Sponsored by Cadence Design Systems

Electrical-thermal co-simulation can dramatically improve the system design process, allowing thermal design adaptation to be done much earlier. The Cadence Celsius Thermal Solver is a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. In this episode of Chalk Talk, Amelia Dalton chats with CT Kao of Cadence Design Systems about how the Celsius Thermal Solver can help detect and mitigate thermal issues early in the design process.

More information about Celsius Thermal Solver