editor's blog
Subscribe Now

Serial Protocol Chameleon

We recently looked at Tektronix’s strategy for their new Veridae acquisition, but we also looked more broadly at their overall focuses, one of which is on serial links. They recently demonstrated a platform for testing such links.

There’s been a tendency for test boxes to be confined to individual protocols or families of protocols; their main point here is the integration of numerous protocols in the one box. Specifically, they list as examples Ethernet, Fibre Channel, Common Public Radio Interface (CPRI), and Serial Front Panel Data Port (FPDP). Or any combination of those.

But they also have a means for users to define their own protocols.

The other thing that tends to create a multiplicity of boxes on the benchtop is the function: pattern generators, for example, are different from analyzers. Their proposal is that a single box can act as protocol analyzer, traffic generator, system stress tester, or bit-error-rate tester – or any combination of those.

But don’t go looking for this just yet on the shelves of your neighborhood protocol analyzer dealer. This was a technology demonstration at ESC Boston. Although, it almost sounds like a product isn’t far behind…

More info in their release… (and hopefully more when released)

Leave a Reply

featured blogs
Jul 1, 2022
We all look for 100% perfection and want to turn our dreams (expectations) into reality as far as we can. Are you also looking for a magic wand to turn expectation into reality? The story applies to... ...
Jun 30, 2022
Learn how AI-powered cameras and neural network image processing enable everything from smartphone portraits to machine vision and automotive safety features. The post How AI Helps Cameras See More Clearly appeared first on From Silicon To Software....
Jun 28, 2022
Watching this video caused me to wander off into the weeds looking at a weird and wonderful collection of wheeled implementations....

featured video

Demo: Achronix Speedster7t 2D NoC vs. Traditional FPGA Routing

Sponsored by Achronix

This demonstration compares an FPGA design utilizing Achronix Speedster7t 2D Network on Chip (NoC) for routing signals with the FPGA device, versus using traditional FPGA routing. The 2D NoC provides a 40% reduction in logic resources required with 40% less compile time needed versus using traditional FPGA routing. Speedster7t FPGAs are optimized for high-bandwidth workloads and eliminate the performance bottlenecks associated with traditional FPGAs.

Subscribe to Achronix's YouTube channel for the latest videos on how to accelerate your data using FPGAs and eFPGA IP

featured paper

3 key considerations for your next-generation HMI design

Sponsored by Texas Instruments

Human-Machine Interface (HMI) designs are evolving. Learn about three key design considerations for next-generation HMI and find out how low-cost edge AI, power-efficient processing and advanced display capabilities are paving the way for new human-machine interfaces that are smart, easily deployable, and interactive.

Click to read more

featured chalk talk

Machine Learning with Microchip

Sponsored by Mouser Electronics and Microchip

Can you design a machine learning application without a deep knowledge in machine learning? Yes, you can! In this episode of Chalk Talk, Amelia Dalton chats with Yann Le Faou from Microchip about a machine learning approach that is low power, includes an expertise in communication and security, and is easy to implement.

Click here for more information about Microchip Technology Machine Learning