editor's blog
Subscribe Now

Write Once, Read Many

When a foundry prepares a process for a designer to use, it’s got to communicate how that process works and how it can be used. Which has to be couched in terms that an EDA tool can use.

Problem is, each foundry has its parameters and such, and each EDA tool has its formats and such. The same information ends up getting done and redone and redone in order to cover all the players.

There have been efforts to corral this to some extent by TSMC (at the very least) with their ixxx (e.g., iDRC) efforts, but those have been “proprietary” even if developed in a more open way.

Si2 is attempting to reconcile this all in their OpenPDK project, which has been underway for quite a while. It’s really a nested effort, incorporating other DRC, DFM, and parametric extraction (PEX, as embodied in their OPEX effort, which shouldn’t be confused as contrasting with CAPEX) projects, to name a few.

This all comes together as a big XML schema that forms an Open Process Specification (OPS). As described at Si2’s recent tech conference, work groups are busily defining parameters and symbols and callbacks and such. The end goal of this, anticipated around the end of 2012, is that automation will allow a single populated OPS to generate the PDKs needed for any of the EDA tools. This separates the information content from the format, the OPS containing the content and a filter essentially skinning it for the EDA tools.

It is noteworthy that the word “open” appears in this context. Things have been gradually changing, but imagine if ten years ago you suggested that the foundries open up… well… anything. Would have been worth a chuckle then, so it represents quite the change of heart that this effort looks to be successful in the not-too-distant future. More on that in a few days…

Leave a Reply

featured blogs
Oct 28, 2021
Spectre 21.1 ISR2 and Virtuoso IC6.1.8 ISR21 introduce the new Voltus TM -XFi Custom Power Integrity Solution, a new transistor-level electromigration and IR drop (EMIR) solution that provides a... [[ Click on the title to access the full blog on the Cadence Community site. ...
Oct 27, 2021
ASIC hardware verification is a complex process; explore key challenges and bug hunting, debug, and SoC verification solutions to satisfy sign-off requirements. The post The Quest for Bugs: The Key Challenges appeared first on From Silicon To Software....
Oct 20, 2021
I've seen a lot of things in my time, but I don't think I was ready to see a robot that can walk, fly, ride a skateboard, and balance on a slackline....
Oct 4, 2021
The latest version of Intel® Quartus® Prime software version 21.3 has been released. It introduces many new intuitive features and improvements that make it easier to design with Intel® FPGAs, including the new Intel® Agilex'„¢ FPGAs. These new features and improvements...

featured video

Simplify building automation designs with MSP430

Sponsored by Texas Instruments

Smart building automation requires simple, flexible designs. With integrated, high-performance signal chain, MSP430 MCUs can enable high-accuracy motion detection, sensing and motor control to take performance and efficiency to the next level.

Click here for more information

featured paper

How to Fast-Charge Your Supercapacitor

Sponsored by Maxim Integrated (now part of Analog Devices)

Supercapacitors (or ultracapacitors) are suited for short charge and discharge cycles. They require high currents for fast charge as well as a high voltage with a high number in series as shown in two usage cases: an automatic pallet shuttle and a fail-safe backup system. In these and many other cases, the fast charge is provided by a flexible, high-efficiency, high-voltage, and high-current charger based on a synchronous, step-down, supercapacitor charger controller.

Click to read more

featured chalk talk

Time Sensitive Networking for Industrial Automation

Sponsored by Mouser Electronics and Intel

In control applications with strict deterministic requirements, such as those found in automotive and industrial domains, Time Sensitive Networking offers a way to send time-critical traffic over a standard Ethernet infrastructure. This enables the convergence of all traffic classes and multiple applications in one network. In this episode of Chalk Talk, Amelia Dalton chats with Josh Levine of Intel and Patrick Loschmidt of TTTech about standards, specifications, and capabilities of time-sensitive networking (TSN).

Click here for more information about Intel Cyclone® V FPGAs