When two chips talk to each other, they do so over a convoluted path that involves signals leaving a driver, going to a pad, up through a wire and other package interconnect, up and down and around along a board trace, and back into and through a package to another pad, finally arriving at the desired input. All along the way they brush up against other signals that may also be switching very quickly. Meanwhile, the power driving the output and input circuits may experience noise (and, in fact, that noise may be different on each chip). When you’ve got a lot of these signals that need to arrive with picosecond precision, such as is required with standards like the latest DDR versions, every part of the path matters.

Sigrity says that the traditional method of doing I/O analysis, using the IBIS models from the two chips, is no longer sufficient, especially when considering power noise and effects such as simultaneous switching noise (SSN). So they’ve just released SystemSI, which analyzes the entire path as a single entity, concurrently considering power noise and SSN as well as inter-symbol interference, crosstalk, reflections, and losses in both the conductors and dielectric. There’s a version for parallel busses and one for serial busses. They claim that it’s the first solution of its kind.

Sigrity uses what they call a “hybrid solver” approach involving both electromagnetic (EM, using both finite element – FE – and method of moment – MOM – approaches) and circuit simulation techniques. Says Leslie Landers, VP of Sales and Marketing, “For example, the hybrid solver assesses planes with FEM and transmission lines with MOM. This EM information is combined with circuit simulation. The benefit of the hybrid approach is in the ability to deliver both accuracy and efficient simulation run times that make it possible to evaluate entire structures (for example, large boards).”

More details in their release…