editor's blog
Subscribe Now

End-to-End Signal Analysis

When two chips talk to each other, they do so over a convoluted path that involves signals leaving a driver, going to a pad, up through a wire and other package interconnect, up and down and around along a board trace, and back into and through a package to another pad, finally arriving at the desired input. All along the way they brush up against other signals that may also be switching very quickly. Meanwhile, the power driving the output and input circuits may experience noise (and, in fact, that noise may be different on each chip). When you’ve got a lot of these signals that need to arrive with picosecond precision, such as is required with standards like the latest DDR versions, every part of the path matters.

Sigrity says that the traditional method of doing I/O analysis, using the IBIS models from the two chips, is no longer sufficient, especially when considering power noise and effects such as simultaneous switching noise (SSN). So they’ve just released SystemSI, which analyzes the entire path as a single entity, concurrently considering power noise and SSN as well as inter-symbol interference, crosstalk, reflections, and losses in both the conductors and dielectric. There’s a version for parallel busses and one for serial busses. They claim that it’s the first solution of its kind.

Sigrity uses what they call a “hybrid solver” approach involving both electromagnetic (EM, using both finite element – FE – and method of moment – MOM – approaches) and circuit simulation techniques. Says Leslie Landers, VP of Sales and Marketing, “For example, the hybrid solver assesses planes with FEM and transmission lines with MOM. This EM information is combined with circuit simulation. The benefit of the hybrid approach is in the ability to deliver both accuracy and efficient simulation run times that make it possible to evaluate entire structures (for example, large boards).”

More details in their release

Leave a Reply

featured blogs
Apr 16, 2024
In today's semiconductor era, every minute, you always look for the opportunity to enhance your skills and learning growth and want to keep up to date with the technology. This could mean you would also like to get hold of the small concepts behind the complex chip desig...
Apr 11, 2024
See how Achronix used our physical verification tools to accelerate the SoC design and verification flow, boosting chip design productivity w/ cloud-based EDA.The post Achronix Achieves 5X Faster Physical Verification for Full SoC Within Budget with Synopsys Cloud appeared ...
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

Power High-Performance Applications with Renesas RA8 Series MCUs
Sponsored by Mouser Electronics and Renesas
In this episode of Chalk Talk, Amelia Dalton and Kavita Char from Renesas explore the first 32-bit MCUs based on the new Arm® Cortex® -M85 core. They investigate how these new MCUs bridge the gap between MCUs and MPUs, the advanced security features included in this new MCU portfolio, and how you can get started using the Renesas high performance RA8 series in your next design. 
Jan 9, 2024
14,036 views