editor's blog
Subscribe Now

Home-Brewed Emulators

When you need to verify test suites that drag on for millions (or billions) of clock cycles, it really helps to run them on some hardware – assuming you need clock accuracy. Otherwise, well, “legacy code” acquires a new meaning: the project you started and passed to your progeny because simulation couldn’t finish in your lifetime.

There are various emulation systems out there, but if you’ve done a lot of work on your own prototype, then redoing the design on an emulator might seem like redundant work.

In the meantime, Aldec has an HES system that conveniently splits into two: a board and the DVM (Design Verification Manager) software. The unique thing is that the DVM environment can be ported to different boards by Aldec. So they can adapt it to your prototype board.

But real verification acceleration requires the SCE-MI 2.0 standard. This allows much more time-efficient transactions to jump back and forth from the host/software side to the board rather than requiring signal-level information to be laboriously transferred. Serious modern emulators support the SCE-MI standard as a matter of course.

So Aldec just announced that version 2011.04, among other things, supports the SCE-MI 2.0 standard, with speeds up to 4 MHz on 10-million-gate designs. This means that you have the possibility of using your prototype board for emulation as an alternative to buying separate emulator hardware. While the DVM software will need to be compared for such things as debug features, price, etc. with other emulation options – and you would need to work with Aldec to have the port done – it’s an option that, as far as I know, isn’t available anywhere else.

More details in their press release

Leave a Reply

featured blogs
Jun 12, 2025
We truly do live in a world that would have been considered to be a far-flung science fiction future only a few short decades ago...

featured paper

Shift Left with Calibre Pattern Matching: Trust in design practices but verify early and frequently

Sponsored by Siemens Digital Industries Software

As integrated circuit (IC) designs become increasingly complex, early-stage verification is crucial to ensure productivity and quality in design processes. The "shift left" verification approach, enabled by Siemens’ Calibre nmPlatform, helps IC design teams to identify and resolve critical issues much earlier in the design cycle.

Click to read more

featured chalk talk

Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff
Sponsored by Synopsys
The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology can enable consistent power efficiency and power reduction.
Jul 29, 2024
246,990 views