editor's blog
Subscribe Now

Home-Brewed Emulators

When you need to verify test suites that drag on for millions (or billions) of clock cycles, it really helps to run them on some hardware – assuming you need clock accuracy. Otherwise, well, “legacy code” acquires a new meaning: the project you started and passed to your progeny because simulation couldn’t finish in your lifetime.

There are various emulation systems out there, but if you’ve done a lot of work on your own prototype, then redoing the design on an emulator might seem like redundant work.

In the meantime, Aldec has an HES system that conveniently splits into two: a board and the DVM (Design Verification Manager) software. The unique thing is that the DVM environment can be ported to different boards by Aldec. So they can adapt it to your prototype board.

But real verification acceleration requires the SCE-MI 2.0 standard. This allows much more time-efficient transactions to jump back and forth from the host/software side to the board rather than requiring signal-level information to be laboriously transferred. Serious modern emulators support the SCE-MI standard as a matter of course.

So Aldec just announced that version 2011.04, among other things, supports the SCE-MI 2.0 standard, with speeds up to 4 MHz on 10-million-gate designs. This means that you have the possibility of using your prototype board for emulation as an alternative to buying separate emulator hardware. While the DVM software will need to be compared for such things as debug features, price, etc. with other emulation options – and you would need to work with Aldec to have the port done – it’s an option that, as far as I know, isn’t available anywhere else.

More details in their press release

Leave a Reply

featured blogs
Sep 19, 2024
I just saw an awesome presidential debate remix video by David Scott (a.k.a. the Kiffness). I'd never heard of David before. I'll never forget him now....

featured paper

A game-changer for IP designers: design-stage verification

Sponsored by Siemens Digital Industries Software

In this new technical paper, you’ll gain valuable insights into how, by moving physical verification earlier in the IP design flow, you can locate and correct design errors sooner, reducing costs and getting complex designs to market faster. Dive into the challenges of hard, soft and custom IP creation, and learn how to run targeted, real-time or on-demand physical verification with precision, earlier in the layout process.

Read more

featured chalk talk

Reliability: Basics & Grades
Reliability is cornerstone to all electronic designs today, but how reliability is implemented and determined can vary widely by different market segments. In this episode of Chalk Talk, Amelia Dalton and Sam Accardo from the YAGEO Group explore the definition of reliability for electronic components, investigate the different grades of reliability offered by the YAGEO Group and the various steps that the YAGEO Group is taking to ensure the greatest reliability of their components.
Aug 15, 2024
16,603 views