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GOWIN’s “Golly Gosh” Low-Cost High-Performance FPGAs

I remember when the first FPGA waved a cheery hello to the world back in 1985. (I know I’ve talked about this before, but there are always new members to the EE Journal Community who weren’t around when many of the technologies we now take for granted originally appeared on the scene.) This little scamp was the Xilinx XC2064, which boasted an 8×8=64 array of configurable logic block (CLB) “islands,” each containing two 3-input look-up tables (LUTs), all presented in a “sea” of programmable interconnect.

Just to make things fun and interesting, users had to define the contents of the LUTs and the connections between the CLBs by hand. Automatic design tools? Don’t make me laugh. At that time, traditional programmable logic devices (PLDs) like PROMS, PLAs, PALs, GALs, etc. were fully deterministic. So much so that, as I recall, their data sheets specified different times from rising and falling edges on their inputs causing rising and falling transitions on their outputs. By comparison, it was almost impossible to even guesstimate the design-dependent timing of an FPGA. The easiest approach was to program the device, measure the real-world timings on the testbench, document them while pretending they were what you were aiming at all along, and then do your best not to change anything.

Oh, the fun we had. To be honest, many of us doubted that FPGAs would ever succeed (we certainly feel silly now). We had no idea that FPGA capacity and performance would increase so rapidly, or that logic synthesis tools were poised to leap onto the stage with a phantastic fanfare of flugelhorns (my ears are still ringing), and that these tools would allow you to specify the timings you required and then do their best to achieve them. The rest, of course, is history—one that I would be more than happy to expound upon had my friend Steve Leibson not already done so in excruciating exhilarating detail in his mega-mini-series of columns here on EE Journal (see How the FPGA Came to Be: Part 1, Part 2, Part 3, Part 4, Part 5, and Part 6).

As an aside, apropos of nothing at all, speaking of the Sound Blocks Kickstarter (we weren’t, but we are now), as I mentioned in my Using Sound Blocks to Make Musical Machines Cool Beans Blog, I’ve already made my $15 pledge for the “Super Early Bird (50% Off)” special, and I’m really hoping to push these guys and gals over their $10,000 goal so I can get to play with Sound Blocks on my PC, so anything you can do to spread the good word would be much appreciated, but we digress…

Many FPGA companies have flowered and faded over the years. Oftentimes, smaller FPGA vendors have been assimilated by larger collectives (“resistance is futile”). As a result, when most non-FPGA-guru electronic design engineers hear the term “FPGA,” their knee-jerk reaction is to think of well-known players like Altera (which was acquired by Intel in 2015 and spun back out as a fully-owned subsidiary earlier this year), Xilinx (which was acquired by AMD in 2022 although said acquisition was originally announced in 2020), Lattice Semiconductor, and Microchip Technology (which acquired Actel and it’s FPGA portfolio). There are, of course, other contenders, but these are the ones most people think of.

As a point of interest, Lattice was almost acquired by Canyon Bridge Capital Partners back in 2016, where Canyon Bridge is a Chinese-backed, Silicon Valley-based private equity firm that’s focused on growing businesses in China and other high-growth Asian markets. However, this sale was blocked by the US government in 2017 because Lattice’s technology is highly applicable to military and aerospace applications. (Phew! We certainly dodged a bullet there [no pun intended]).

As a related point of interest, several semiconductor startups in China have been dipping their toes in the FPGA waters in recent years (see Steve Leibson’s FPGAs: Made in China column). In some cases, this serves to get around US and European export restrictions. Another very real consideration—one that was really brought to the fore by the COVID19 pandemic—is that of supply chain problems, which are mitigated from China’s perspective by having home grown semiconductor fabs and fabless semiconductor companies.

All of which leads us to a very interesting company called GOWIN Semiconductor. To be honest, I didn’t know as much about these little scamps as I should. Fortunately, I just had a very interesting conversation with Mike Furnival (Vice President of International Sales), Daniel Fisher (Director of International Marketing), and Andrew Dudaronek (Marketing Engineer), who were kind enough to bring me up to speed.

We chatted for yonks and yonks (that’s a lot of yonks), but I’ll try to cut a long story short, which is opposite to the way I usually do things (I learned my overly enthusiastic and ramblingly longwinded communication skills at my mother’s knee). In a crunchy nutshell, GOWIN was founded in 2014, they saw their first Silicon in 2015, and enjoyed their first revenues in 2017, all of which is pretty darned fast, let me tell you! In fact, they currently bill themselves as “The World’s Fastest-Growing FPGA Company,” and who are we to argue?

GOWIN was founded by two Chinese Americans—Jason Zhu (CEO) and Dr. Ning Song (President)—both of whom were senior design managers at Lattice at the time (well, until they left Lattice to found GOWIN). Although Altera and Xilinx have FPGA families that span the spectrum from low to high, it’s generally accepted that their hearts and minds circa 2014 were focused on the highest-end devices. Meanwhile, the chaps and chapesses at Lattice were happily carving out a position for themselves in mid-range FPGA space (where no one can hear you scream).

Jason and Ning firmly believed that there was a market play in the low-density FPGA space that was being largely ignored by the other companies. I always think of America as a place where one can get things done, but Jason and Ning found it hard to gain access to funding over here. Since there was both a market opportunity and access to funding in China, that’s where GOWIN kicked off. Today, GOWIN has R&D centers in China and Hong Kong, and international sales offices in China, Hong Kong, Korea, Vietnam, the UK, and the USA.

But wait, there’s more… GOWIN kicked off with low- and medium-density offerings in the form of their LittleBee (a.k.a. GW1N series) 55nm eFlash-based (1K to 9K LUTs) devices and Arora (a.k.a. GW2A series) 55nm RAM-based (18K to 55K LUTs) parts, respectively. Their initial offerings had their own pinouts. However, the folks at GOWIN soon found themselves fielding requests for pin-compatible replacements for parts from other FPGA vendors, including components that were going end-of-life (EOL) and devices that were hard to find.

Thus, it wasn’t long before the guys and gals at GOWIN found themselves fielding pin-compatible (well, ball-compatible) replacements for FPGAs from Altera, Lattice, and Xilinx. As you can imagine, this placed them in a perfect position to weather any supply chain storms caused by things like trade wars, tariffs, and worldwide pandemics. Apart from anything else, many users get a warm glow when they know they have a second source for something.

 Products past, present, and future (Source: GOWIN)

Now, it’s important to note that “pin compatibility” is not the same as “functional compatibility”—we aren’t talking about a cookie-cutter copy here. On the other hand, at this level of device, if you compare parts with, say, 50K LUTs from any of the vendors, you’ll typically find that they have the same number of PLLs, around the same quantity of block RAM (BRAM), and the same collection of features and functions. All of which means that porting a design—while not a simple recompilation—won’t bring you to your knees (figuratively or literally).

Today, GOWIN’s FPGAs are being used around the world in a wide variety of applications and markets, including industry (servo control, motion control, PLCs, industrial buses, industrial cameras, industrial printers, IO modules, 3D printers, renewable energy, utilities [gas, electric], security, instrumentation, etc.), automotive (intelligent cockpits, multi-screen displays, local dimming, augmented reality head-up displays (AR HUDs), assisted driving, electronic rearview mirrors, motor control, smart taillights, etc.), consumer (cell phones, smart tablets and pads, electronic ink screens, VR/AR glasses, drones, TV ambient lighting, etc.), and others.

One of the reasons for our chat, in addition to formally introducing me to GOWIN, was for Mike, Daniel, and Andrew to tell me about the latest and greatest addition to their line-up in the form of the Arora V (a.k.a. GW5A series) 22nm RAM-based mid-density FPGAs (15K to 138K LUTs). In addition to boasting an ultra-low-power SRAM 22nm process from TSMC, these bodacious beauties flaunt hard 2.5Gbps MIPI cores (both D-PHY and C-PHY), hard PCIe cores, and hard 12.5Gbps SerDes cores, along with Arm Cortex-M4 or RISC-V processor cores and in-package 1333Mbps DDR3 memory. Even better, in addition to application solutions (reference designs) and development kits, all these devices come with access to freely licensed IP and freely licensed EDA tools. What’s not to love?

Hmmm. Well, since you ask, one question that popped into my mind is that China and America aren’t exactly bosom buddies at this moment in time. I wondered aloud if this threw something of a spanner into the works (or a wrench if you’re American). The GOWIN team responded that (much like your humble narrator) they actually represent the best of all possible worlds. First, they reap the benefits of being based in China, which include low costs and access to highly-trained personnel. Second, you get a “can-do” mindset coupled with the flexibility inherent in a smaller company, thereby enabling them to rapidly respond to changing customer needs and evolving market requirements. Third, and this is the big dollop of metaphorical cream on top of the allegorical cake, you get US-style management coupled with US-like corporate responsibility following US-mandated export control. Basically, everything about the company and the way they go to market internationally is based on the US way of doing things.

The fact that GOWIN is a China-based company that adheres to US export controls is something that will take me some time to wrap my brain around (How…? Suppose…? What if…?). In the meantime, while I’m mulling this noteworthy nugget of knowledge in my poor old noggin, do you have any thoughts you’d care to share on anything you’ve read here?

10 thoughts on “GOWIN’s “Golly Gosh” Low-Cost High-Performance FPGAs”

  1. Hi Max,

    Interesting article – thank you. I had reason to take a quick peek at GOWIN some months ago and was impressed. What your article mentions but doesn’t emphasize is the availability of freely licensed IP and EDA tools. My takeaway impression was that GOWIN could really lower the entry barrier to FPGA design. I have been too busy to follow this up but when I have a free tera-picosecond or so I will pursue this and try to get my hands on some kit. As you mention the top players are going for the high end but I agree that there is plenty left in the mid-range market.

    1. During our conversation they mentioned a 30-cent FPGA — I should have pursued that further (which part, how many to get that price break), but they did say they are focused on the combination of cost and performance.

  2. Interesting product. Back in the day, chip pinouts were important to avoid having to re-design the printed circuit board when design tweaks were introduced to improve function/performance. The 16V8 from Lattice and the 22V10 from AMD were pin compatible to the PAL products from MMI.
    When CPLDs arrived, Altera’s Max 5K/7K families sucked up a bunch of PAL and 16V8/22V10 business, though not pin compatible. Max had a bit of a flaw in that design tweaks resulted in frequent printed circuit changes. Xilinx arrived with the XC9500 family CPLDs that had pin locking as their key feature. This meant the chips would keep their pinouts after multiple design tweaks. One ad they used just showed a hand grenade and stated that pin locking can be very important!

    1. “One ad they used just showed a hand grenade and stated that pin locking can be very important!” I remember Altium did a really funny video about an FPGA designer called Dave — it was Friday night and he was just about to leave for a date with a beautiful girl when he discovered the PCB guy had changes his pinouts. That reminded me of a Cadence video along the “Roll over Beethoven” theme with fantastic music and loads of people dancing and prancing in period costume (that production must have cost them a fortune). I just tried to find these videos on YouTube to no avail — hopefully someone will read this and post links to we can see them again.

  3. “chip pinouts were important to avoid having to re-design the printed circuit board”
    An advantage of programmable logic is that the PCB designer has the freedom to swap pin assignment in order to make layout easier and possibly eliminate extra PCB layers. This was always difficult for PCB designers to comprehend that they could change the chip design by recompiling it to a more convenient layout.

    1. The fact that FPGA pinouts can be swapped can be both a blessing and a curse — it’s great when everyone (PCB and FPGA teams) get together agree on a pinout early in the process and stick to it — but it can be a real pain for one team if the other team makes unexpected changes downstream because these changes may benefit one team while thwacking the other team soundly in the nether-regions.

      1. ” fact that FPGA pinouts can be swapped”, right confusion is easy to happen unless PCB designer and chip designer understand the swap and stay in sync.

  4. Hi Max,
    Great article I have been messing about with these Gowin FPGA’s for some time and with some success , which we all know could be hilarious to others seeing my efforts in the past.
    What I have found is that Lushay Labs do some excellent tutorials on using the Tang Nano series of Gowin FPGA.
    In the Lushay labs tutorials they show how to use the open source tools to work with the Gowin fabric.
    The only down side I can say to using the Gown tools is they can be a tad difficult to get programmed using Windows 10 & 11.

    1. Hi Crusty — it’s great to hear from you — how is life at Crusty Mansion with Mrs Crusty? Thanks so much for your feedback on Gowin’s FPGAs — it’s great to hear from someone I know who’s using them.

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