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How the FPGA Came To Be, Part 6: Actel’s FPGA Story

Late in 2021, I published a five-part series titled “How the FPGA Came To Be” (referenced below). That series chronicled the development of programmable logic from the earliest days of Harris Semiconductor’s programmable diode arrays and continued through the development of bipolar PROMs, the Signetics 82S100 FPLA, MMI’s original bipolar PALs, CMOS PAL devices from Altera and Lattice Semiconductor, and finally the introduction of the first FPGA by Xilinx in 1985. However, that series omitted one important player in the FPGA game that was founded in 1985: Actel. I recently had the opportunity to interview one of Actel’s founders, Dr Esmat Hamdy, for a Computer History Museum Oral History, who provided the missing link. Here is Actel’s FPGA story.

As the son of an Egyptian diplomat, Esmat Hamdy grew accustomed to moving from one country to the next every two years. He remembers that the last two countries his father served in were Bolivia and Argentina. He also remembers that he was not able to make any long-term friends during this period in his life due to the frequent relocations. Consequently, Hamdy did not relish the life of a diplomat. His grandfather had been an engineer for the railroad in Cairo and told Hamdy, “Esmat, I want you to invent something.” Taking his grandfather’s advice, Hamdy decided to become an engineer and went to Cairo University at the age of 16 to study engineering.

The engineering program at Cairo University was a 5-year program, so Hamdy graduated at the age of 21. The first year of the program was a general introduction to engineering. After the first year, students were asked to choose a branch of engineering, and Hamdy chose electrical engineering, specializing in electronics rather than the alternative: power generation and transmission. At that time, electronics classes covered vacuum tubes, so Hamdy learned about tube diodes and triodes. Only in his final year did Hamdy take a class in semiconductors.

After graduating, Hamdy took a position as an assistant teacher at nearby Helwan University and started working on his master’s degree at Cairo University. He chose thin-film deposition for the subject of his master’s thesis and developed metrology to monitor the thickness of thin-film aluminum in real time as it was being deposited. Once he’d earned his master’s degree, Hamdy started looking for a university for his PhD degree. He chose the University of Waterloo in Canada because some of his friends from Cairo went on to Waterloo. His PhD advisor at Waterloo suggested that Hamdy earn a second master’s degree as a backup plan in case he was not able to finish his PhD for some reason. That way, he’d have a North American master’s degree to back up his master’s degree from Cairo University. Hamdy started working on his Waterloo master’s degree in 1975 and his PhD in 1977. He’d earned both degrees by 1980.

By then it was time for Hamdy to find an employer and enter the workforce. He applied to six companies, including Xerox, Philips, Fairchild Semiconductor, Texas Instruments, Intel, and Hewlett-Packard (HP). He received offers from all of them. Hamdy decided that the best candidates were Intel and HP. Intel was the brash semiconductor startup that had introduced the first commercial DRAM, EEPROM, and microprocessor all in one miraculous year. HP was the legendary systems and technology company started by Bill Hewlett and Dave Packard in 1939. Both companies offered the same starting salary, so Hamdy chose Intel because the company’s offer included stock. HP’s offer did not.

Hamdy joined Intel’s DRAM group in Oregon. He initially worked on semiconductor process technology for the company’s 64kbit NMOS DRAM and then started working on a 256kbit CMOS DRAM, about the time that Intel decided to exit the DRAM business in 1985. Hamdy stayed with Intel after the company’s DRAM divestiture. His next major assignment was to get the CMOS 80386 microprocessor to yield. The 80386 had been designed at Intel’s facilities in Santa Clara, California, but it was not yielding well using Santa Clara’s manufacturing process. Hamdy’s team in Oregon modified the process technology and device physics without changing the design and were able to boost yields of the 80386 to acceptable levels.

At the time, Hamdy’s supervisor at Intel was Amr Mohson, who wanted to start his own semiconductor company. Mohson enlisted Hamdy and Abbas El Gamel, a Stanford University professor who’d worked at LSI Logic, which was an early pioneer for mask-programmed gate arrays. The two big problems with mask-programmed gate arrays were the non-recurring engineering (NRE) costs and long turnaround times before parts became available. Meanwhile, programmable logic devices, including MMI’s PALs and complex PLDs (CPLDs) from Lattice and Altera, were running out of steam. Designers wanted the field programmability of PLDs, but they needed more logic gates in the package. This semiconductor niche was empty at the time, so the three entrepreneurs decided to found a company that focused on the development of field-programmable gate arrays (FPGAs). That company would become Actel.

From the beginning, Actel’s founders planned to develop an antifuse technology for the FPGA’s programmable interconnect. An antifuse has a high resistance until you program it. After programming, the antifuse exhibits a much lower resistance. The original plan was to develop a metal-metal antifuse that would connect traces between two metal layers on the IC. However, such an antifuse requires very flat metal layers, which could not be manufactured until the advent of chemical-mechanical polishing (CMP).

As an interim step, the Actel design team placed the antifuse between the IC’s polysilicon and diffusion layers. Actel called this antifuse a “programmable low-impedance circuit element,” or PLICE. A 10nm thin film of oxide-nitride-oxide separated the polysilicon layer from the diffusion layer. A programming pulse would cause the thin-film layer to switch to a more conductive state.

Initial results with Actel’s PLICE antifuse were disastrous. A programmed antifuse exhibited an “on” resistance of 10Kohms to 20Kohms, which was far too high. The Actel team went into disaster recovery mode, and Hamdy recalls meeting twice a day for three months straight trying to develop a solution to this problem. During that time, he says he lost 20 pounds.

In the end, the solution was to heavily dope the polysilicon layer with arsenic. During programming, the applied electric field and generated heat would drive the arsenic into the thin-film insulation layer, creating a reliable antifuse with an “on” resistance of 500 ohms, which was acceptable for shorter tracks on the IC. The resistance was still too high to drive long tracks, but a programming pulse using higher currents could reduce the “on” resistance to as low as 200 ohms. When CMP became available as a process step, Actel switched to a metal-metal antifuse, and the heavy arsenic doping was no longer required.

Actel shipped its first FPGAs in 1988. Xilinx had been shipping parts that the company called “Logic Cell Arrays,” based on SRAM programmability, since 1985. These parts were the first FPGAs on the market. Altera had been shipping EPROM-based CPLDs since 1983 and was eventually forced to move into the FPGA market after 1988, when CPLDs became impracticably large. According to Actel’s former CEO, John East, Actel was the first company to use the term FPGA.

Because the antifuses used in Actel’s FPGAs were immune from single-event upsets (SEUs), the technology was readily adopted by the military and aerospace industry. In his oral history, Hamdy said, “There is no satellite either made in Japan, or in Europe, or in the US, which does not have our parts. The Mars Rover has our parts in it.” Actel’s initial semiconductor foundries were Texas Instruments and Mitsubishi Electric. However, Actel also developed a relationship with Loral, a military contractor with its own radiation-hardened process technology, so Loral also became a foundry for Actel and created truly rad-hard FPGAs based on Actel’s designs.

Actel’s antifuse was both a blessing and a curse. The blessing was the antifuse’s SEU immunity, which was highly desirable for certain products with critical missions. The curse was that the antifuse was not scalable. In his article titled “From AMD to Actel (to Microchip),” John East wrote, “… antifuses required a difficult custom fab process that prohibited us from ever being on an advanced process node (Xilinx was always on the most advanced process nodes.)”

East eventually decided to retire from Actel. Microsemi, a semiconductor company that specialized in component sales to the Mil/Aero market, bought Actel in 2010. Eight years later, Microchip purchased Microsemi and added Actel’s products to the company’s product portfolio. Hamdy is now a Senior Fellow at Microchip. He’s still in the FPGA game.

Previous articles in this series:

How the FPGA Came To Be, Part 1

How the FPGA Came To Be, Part 2

How the FPGA Came To Be, Part 3

How the FPGA Came To Be, Part 4

How the FPGA Came To Be, Part 5

Reference

John East, “From AMD to Actel (to Microchip),” SemiWiki, September 2, 2019

2 thoughts on “How the FPGA Came To Be, Part 6: Actel’s FPGA Story”

  1. Great series Steven, on both this and the history of EDA. We have something in common, both having worked for Cadnetix and both being Steven’s though I worked as an Applications Engineer in the UK…

    One of the problems biggest problems we had with early larger FPGAs, especially a large mobile phone base station provider who was making huge bleeding edge PCBs covered in FPGAs and specialist processors, was that to get the best use of the macrocells, it was necessary to change the pinouts of the FPGAs on each FPGA iteration. This then needed the schematics and PCBs to be manually fixed – a tough job on these boards. I wrote a monster AWK script that given the FPGA design reports from Xilinx, Actel, Altera and Lattice, would scan the files for the pin-outs, and build a new layer of hierarchical schematic with a symbol connecting the named pins above to the new PCB pins below. All this in AWK (!) but it reduced turnaround time to a few minutes from several hours per FPGA.

    1. Hiya Duke, Duke, Duke, DukeofEarl. My good friend Robert Bielby, who was also my first manager at Xilinx, explained to me how tone deaf the early FPGA software developers were about pinning the I/O pin definitions between iterations of an FPGA configuration. I’m glad you found a workaround. I think things are better now in that aspect, but cannot guarantee it. Meanwhile, since you are also a Steven, I recommend the old movie “The Tao of Steve.” It’s an important part of any Steve’s movie experience. –Steve

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