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Fast and Accurate?

It’s a song as old as time: if the tool takes too long to run, then run a less accurate version early on, and just use the accurate version at the end.

In other words, speed comes at the expense of accuracy.

So I have to say that I was a bit confused and suspicious when Atrenta claimed that their new Fast Lint didn’t sacrifice any accuracy. A conversation with their Mike Gianfagna cleared the picture up a bit.

You see, Atrenta says that they live and breathe by … Read More → "Fast and Accurate?"

Indoor “GPS”

Location-based services have become popular as smartphones are able to listen to the faint GPS (or GLONASS) signals and figure out where you are in relation to other things. But roofs and walls can block out those satellite signals, leaving you on your own once you enter a building.

Now, many mapping applications are intended to get you to a building, so, once you’re there, well, you’re there – mission accomplished. But, as any of you that go to conventions will know, even within the building, it can still take a … Read More → "Indoor “GPS”"

Another Tool in the Cloud

We saw recently that Protecode added an online capability for a quick audit of software on a one-off basis. It involves upload by a user, automated analysis by Protecode-side tools, and then a manual review at Protecode just to make sure everything looks right. The tools themselves are hidden from the user.

They’ve now gone one step further and offered their tools outright through the cloud. To understand their motivation, it helps to review what their tools do. They analyze software – … Read More → "Another Tool in the Cloud"

Full-Wave 3D IC Sign-Off

I mentioned Nimbic’s cloud moves the other day, but that’s just about the delivery vehicle for their tools. With respect to the tools themselves, their message at DAC this year was that they can now handle the package analysis needs of 3D IC projects with sign-off-level quality.

Those of us that are used to thinking in terms of die analysis might be given pause: multiple dice at advanced technology nodes, full wave, no shortcuts… wow, immense, right? Think about the … Read More → "Full-Wave 3D IC Sign-Off"

Movea Comments

I recently did a blog post on sensor fusion, and I included some input I received from Dave Rothenberg of Movea. He had some follow-on comments clarifying some points against my interpretation of our conversation. Unfortunately, I discovered that we have had some issues with our blog comments being visible. That has been fixed, so I wanted to post a new note here with a link to his comments since they’re moved off the front page now.

I thank Dave for his patience as we … Read More → "Movea Comments"

Working Forward

You may recall that Vennsa’s OnPoint tool takes the results of verification and helps identify errors and possible causes. The tool’s early focus was on identifying suspect issues and letting you work from there.

Last year around DAC time, we noted that they took things a step further to suggest possible fixes (but you had to confirm whether they truly were fixes) and to do a … Read More → "Working Forward"

Privatizing the Cloud

Last year, Nimbic put a lot of focus on their cloud implementation – to the point of changing the company name (erstwhile Physware). This year, part of their focus has been on implementing their tools on so-called “private clouds”: making use of the large server farms that some companies have. The drivers for this are the existence of these farms – why not use them? – as well as the usual security concerns that, while not universal, still dog the whole public cloud question.

But this now starts to sound a whole lot like an … Read More → "Privatizing the Cloud"

Assembling an SoC Architecture

Planning an SoC has never been easy. As chip design has moved from mostly-from-scratch design to mostly-IP (even if internal), and as the size of the chip has grown, architectural decisions have to be made with loose back-of-the-envelope estimates, since much of the detailed implementation decisions aren’t made at that point. IP in particular can vary wildly depending on the source. And, while this sounds somewhat less likely, given the strong connections between design houses and foundries, you might even want to have a bake-off between foundries if that is part of the decision process.

Read More → "Assembling an SoC Architecture"

A New 3D IC Approach

While 3D ICs have been sexy for a while, actually building them has been a bit more of a stately process than simply talking about them. The details house numerous devils that must be worked out in order for the process to be manufacturable.

One way that TSMC is approaching it is through what they call CoWoS: Chip on Wafer on Substrate. This is a 2.5-D process, really: the multiple dice are mounted on a silicon interposer. The catch is that this happens while the interposer wafer is still whole. This allows known-good dice to be mounted … Read More → "A New 3D IC Approach"

Virtualizer and HAPS Shake Hands

Numerous systems tend to get used for verifying SoCs, and, with software now in the picture, the range is extended even further. We’ve talked before about the use of simulation, virtual prototypes, emulation, and prototyping as ways of getting both hardware and software to work, and to work together. Including their unification.

Synopsys recently took a move towards unification by bringing their Virtualizer virtual platform tool and their HAPS prototyping tool closer together. What this is means is that a design can … Read More → "Virtualizer and HAPS Shake Hands"

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