editor's blog
Subscribe Now

Virtualizer and HAPS Shake Hands

Numerous systems tend to get used for verifying SoCs, and, with software now in the picture, the range is extended even further. We’ve talked before about the use of simulation, virtual prototypes, emulation, and prototyping as ways of getting both hardware and software to work, and to work together. Including their unification.

Synopsys recently took a move towards unification by bringing their Virtualizer virtual platform tool and their HAPS prototyping tool closer together. What this is means is that a design can be implemented with some parts in Virtualizer and some in HAPS and the two systems can talk to each other while running.

They actually run the SCE-MI 2 interface (traditionally found in the emulator-to-host connection), running over their UMRBus. This allows transactors to speed the interchange of data.

The architecture is very AMBA-centric; much of their DesignWare catalog relies on AMBA, and AMBA is popular, so this isn’t a big surprise. They’re open to other busses on an “ask us and we’ll consider it” basis.

The actual use of the tools isn’t so integrated. The two sides have separate programs that you run to manage them – there isn’t one unified interface that can talk to both sides. But this is partly due to the fact that they don’t traditionally see one person doing the whole thing. In the early stages, system integrators/architects would use the Virtualizer side and FPGA guys would implement the HAPS side; they would tag-team to get it up and running. Once that’s all done, then software programmers could use it (using computers more moderate than those required for the FPGA-building tools, for instance). So a single console might not have an associated use case.

The design partitioning process is also manual (although they could see the future possibility of tagging a design to automatically build the virtual and FPGA sides). Cross-triggering between the two sides is rudimentary.

This capability will be generally available in August. Why announce when they did? I’m guessing because they couldn’t talk the DAC guys into rescheduling the conference to August…

You can find more info in their release

 

Leave a Reply

featured blogs
Jan 24, 2020
Someone has created a song by taking Pi, assigning each number to a note, and adding harmonies. The result is strangely captivating....
Jan 24, 2020
[From the last episode: We looked at the different ways memory can be organized in different kinds of systems.] Let'€™s look at a scenario: you run a restaurant, but you'€™re short on funds to hire people. So you'€™re your own chief cook and bottle-washer. You do everyt...
Jan 23, 2020
Embedded design trends typically revolve around three main ideas: faster data rates, smaller form factors and cost-effective solutions. Those design trends drive the theme for the 2020 Embedded Tech Trends forum: The Business and Technology Forum for Critical and Intelligent ...
Jan 22, 2020
Master the design and verification of next gen transport: Part One – Overview Master the design and verification of next gen transport: Part Two – High-Level Synthesis Master the design and verification of next gen transport: Part Three – Functional Safety M...

Featured Video

Automotive Trends Driving New SoC Architectures -- Synopsys

Sponsored by Synopsys

Today’s automotive trends are driving new design requirements for automotive SoCs targeting ADAS, gateways, connected cars and infotainment. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet such new requirements and accelerate design time.

Drive Your Next Design to Completion Today with DesignWare IP® for Automotive SoCs