Planning an SoC has never been easy. As chip design has moved from mostly-from-scratch design to mostly-IP (even if internal), and as the size of the chip has grown, architectural decisions have to be made with loose back-of-the-envelope estimates, since much of the detailed implementation decisions aren’t made at that point. IP in particular can vary wildly depending on the source. And, while this sounds somewhat less likely, given the strong connections between design houses and foundries, you might even want to have a bake-off between foundries if that is part of the decision process.
A small company called Chip Path launched a site at DAC that allows architects to use a browser-based architecture tool to describe the intended function of a chip, and then map that to different foundries or IP blocks or fundamental platform architectures – SoC, FPGA, etc.
While this probably sounds obvious in the abstract, the details of doing this sort of high-level advanced planning have always been difficult. None of the pieces were originally designed to talk to each other – two identically-functioned (at a high level) IP blocks may have incompatible interfaces, for example. They’ve got what they call a “connection network” – a collection of items that have been designed to interconnect easily. These address the overall SoC interconnect scheme (NoC or fabric); streaming connections; interrupts; memory maps; and reset/control, clock, and power networks.
They have created a number of different “portals” that reflect the different things you might be looking for. Some are multi-vendor, for evaluating different foundries; others are “branded”. The SoC estimation, IP search, and FPGA fitting tools are free; they also sell other tools.
As you might suspect, the company shares roots with ChipEstimate, now owned by Cadence. But today’s problem is more complex than that of ChipEstimate back in the day. At the same time, the metaphor they use for explaining what they’re doing harkens back to something more traditional: building a car. They’re treating an SoC as a similar beast, with a list of components to choose from. This more than anything else reflects the role of IP today; such a component-oriented approach would have made much less sense in the past, when so much had to be created from scratch.
You can find out more in their release…
