Using Machine Learning to Optimize FPGA Layout and Timing
As usual, I’m amazed by how fast and how far things have changed in my own lifetime. When I started my career in electronics and computers in 1980, we thought simple programmable logic devices (PLDs) were pretty darned cool, not least that their creators managed to wring so many acronyms out of the same small … Read More → "Using Machine Learning to Optimize FPGA Layout and Timing"