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The Freedom to Innovate: Arteris and the Rise of RISC-V

by Amelia Dalton
The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. In this week’s Fish Fry podcast, Frank Schirrmeister from Arteris and I explore how to enable better architecture optimization, manage different protocols with ease, and reduce interconnect area plus power consumption with network-on-chip IP.  Also this week, I check out new … Read More → "The Freedom to Innovate: Arteris and the Rise of RISC-V"


Blinded by the Light

by Max Maxfield
Do you remember the song Blinded by the Light? This composition, which was originally written and recorded by Bruce Springsteen, first appeared on his 1973 debut album, Greetings from Asbury Park, N.J. Bruce is, of course, a legend. As awesome as his rendition is, however, I will always associate Blinded by the Light with Manfred … Read More → "Blinded by the Light"




The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster

by Amelia Dalton
Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs. We also discuss the details of Arteris’ FlexNoC 5 Physically Aware Network-on-Chip IP, and how a physically aware NoC can not only help you address … Read More → "The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster"

Flex Logix configurable hardware IP for AI and DSP workloads fuses FPGAs, tensor units, and software

by Steven Leibson
Today, we’re going to talk about AI, DSP, FPGAs, IP, and SoCs. Normally, these things don’t all go together. Certainly, FPGAs have been used to implement AI and DSP algorithms, although AI and DSP algorithms generally involve different sorts of computations. (See “A Brief History of the Single-Chip DSP, Part II .”) DSP designs have … Read More → "Flex Logix configurable hardware IP for AI and DSP workloads fuses FPGAs, tensor units, and software"


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