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Software Validation News

LDRA and PRQA both had news at ESC last week. As a reminder, LDRA focuses on the traceability and certification of software, especially software targeted for safety-critical and secure applications. PRQA, on the other hand, prides itself in its deep, detailed code analysis, looking for potential bugs or other problems.

LDRA announced the ability to provide traceability from requirements all the way to object code. It’s that last mile to object code that’s new. The idea is to be able to document that all of the executable code can be traced to a … Read More → "Software Validation News"

What Goes Around

Sitting through iSQED presentations on single-event-upset-tolerant circuits, I couldn’t help but notice the recurrent C2MOS moniker being tossed about. It was unclear to me whether it was stimulating some old, moldy memory or if that was just my imagination.

Some subsequent poking around to learn more proved harder than I expected. The term is tossed out here and there, but it was actually really difficult to confirm what it stands for: Clocked CMOS.

And then I saw … Read More → "What Goes Around"

Shine a Light

Light is full of energy; it’s just that we can’t do much with that energy directly. Whether we’re trying to use the energy to power our world or simply to detect the light itself, we have to extract it. This typically means converting the light to some other more useful form of energy.

There are two fundamental kinds of light conversion: ones that turn light into other light and ones that turn light into electric current … Read More → "Shine a Light"

Xilinx’s Crossover

Xilinx announced their new Zynq family a while back, and now they’re working the positioning to further clarify why it’s different from past processor+FPGA combo chips. At Mentor’s U2U, Xilinx CTO Ivo Bolsens described Zynq as a “crossover” chip, sharing the characteristics of an FPGA, ASSP, and ASIC.

And here’s what he said makes the critical difference: coherency. An FPGA typically resides outside the processor’s known realm, and is responsible for managing its … Read More → "Xilinx’s Crossover"

An Engineer’s Engineer

On the lighter side of things, ESC opened yesterday with a “fireside chat” with Apple co-founder Steve Wozniak, introduced as an engineer’s engineer (and if you don’t know who he is, “you’ve got issues.”)

What got spontaneous applause from the audience were simple populist pronouncements on:

  • Education. He’s clearly not a fan of our factory classrooms where “different” thinkers are herded back onto the duly designated path of “right” thinking, which is why he recommends OpCentral online learning.
  • Patent … Read More → "An Engineer’s Engineer"

Monopoly as the Efficient Model

Mentor CEO Wally Rhines gave a keynote presentation at the recent U2U event and, once you connected all the dots in the presentation, he seemed to make a startling suggestion: that industries with monopolies are more efficient than those with many competitors.

Of course, that’s not exactly how he said it. Rather than talking in terms of monopoly versus competition, he worded it as specialization versus generalization, and the point is that specialization is more efficient.

He used Alcoa as an example. At one time, there was no one but Alcoa for … Read More → "Monopoly as the Efficient Model"

Get Wreal

When analog design discussions turn to simulation, especially when they involve Cadence, one inevitably comes up against the unfortunately-named concept of the “wreal” type. I say “unfortunately” because, pronounced with standard English rules, it’s pronounced “real,” providing no audible distinction from the “real” type. So it’s typically pronounced “double-you-real.” (Or occasionally you’ll hear “wuh-real.& … Read More → "Get Wreal"

DDR3 System On-and-Around the Chip

We saw the other day that Cadence was being aggressive with the memory controller IP from their Denali side. They’re actually trying to create a wider-scoped solution by providing a PCB package that ties in well with their DDR3 memory controller IP.

DDR memory timing is simply nuts, and board layout is critical. Everything matters. So the DDR3 Design-in kit contains the memory controller I/O and IC package model, timing/duration model, connector model, memory model, DIMM topology, and electrical constraints for the controller … Read More → "DDR3 System On-and-Around the Chip"

Vertical or Horizontal?

Once upon a time, Silicon Valley was all about the technology. You developed a skill at something and then applied it to anything that would give you an edge over someone else.

So, for instance, if you’re a company like Wolfson, with a knack for developing analog front-ends for consumer items, then you might do a wide range of them for things like, oh, imaging, audio, etc.

They call that “horizontal” marketing.

But that fell out of favor. Maybe engineers got too busy. Maybe someone had a marketing book … Read More → "Vertical or Horizontal?"

Selling What?

Reading Jim Turley’s article about business models got me thinking about FPGA and EDA companies.  

Yeah, I know. What’s new?

We’ve talked a lot about how EDA companies struggle to find a business model that earns them their fair share of the loot that comes from electronics.  The full-fledged, modern EDA industry has been around for about three decades and… they still drive a huge portion of the technology while reaping a tiny fraction of the rewards.

The fundamental reason for this, I believe, is that they’ … Read More → "Selling What?"

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