editor's blog
Subscribe Now

DDR3 System On-and-Around the Chip

We saw the other day that Cadence was being aggressive with the memory controller IP from their Denali side. They’re actually trying to create a wider-scoped solution by providing a PCB package that ties in well with their DDR3 memory controller IP.

DDR memory timing is simply nuts, and board layout is critical. Everything matters. So the DDR3 Design-in kit contains the memory controller I/O and IC package model, timing/duration model, connector model, memory model, DIMM topology, and electrical constraints for the controller and memory.

While it ties in well with their DDR3 controller IP, it’s modular enough to detach that and still be of use with someone else’s controller IP.

More info in their Allegro press release

Leave a Reply

featured blogs
Jun 26, 2019
The analog/mixed-signal lunch at DAC got moved to Monday this year, since we had made the Spectre X Simulator announcement that morning. For details on that, see my post Spectre X: Same Accuracy, New... [[ Click on the title to access the full blog on the Cadence Community s...
Jun 26, 2019
The 15th annual Manufacturing Leadership Awards Gala, by the National Association of Manufacturers, took place on June 12, 2019. The Manufacturing Leadership Awards honor manufacturing companies and individual manufacturing leaders that are shaping the future of global manufa...
Jun 25, 2019
Over my 25 plus years of being a PCB designer I could not imaging going back to designing a PCB like I did in the late 90’s or even early 2000’s.  New technology is always being added to tools we use that helps simplify our job.  The key is making sure you'€™r...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...