editor's blog
Subscribe Now

Xilinx’s Crossover

Xilinx announced their new Zynq family a while back, and now they’re working the positioning to further clarify why it’s different from past processor+FPGA combo chips. At Mentor’s U2U, Xilinx CTO Ivo Bolsens described Zynq as a “crossover” chip, sharing the characteristics of an FPGA, ASSP, and ASIC.

And here’s what he said makes the critical difference: coherency. An FPGA typically resides outside the processor’s known realm, and is responsible for managing its own memory – and for keeping the contents consistent with the main CPU memory if necessary.

In Zynq, by contrast, the FPGA gets access to the main memory. That means less data copying, since the processor can simply send a pointer to the FPGA for some accelerated function. The FPGA and the CPU are, more or less, peers – it’s multicore with shared memory, only with one of the cores being an FPGA. And the FPGA doesn’t need its own memory manager.

As subtle as that seems, it can make a big difference in how you conceptualize the interplay between CPU and FPGA. And, presumably, removes some glue logic and speeds performance.

Leave a Reply

featured blogs
Jan 17, 2022
Today's interview features Dajana Danilovic, an application engineer based near Munich, Germany. In this video, Dajana shares about her pathway to becoming an engineer, as well as the importance of... [[ Click on the title to access the full blog on the Cadence Community sit...
Jan 13, 2022
See what's behind the boom in AI applications and explore the advanced AI chip design tools and strategies enabling AI SoCs for HPC, healthcare, and more. The post The Ins and Outs of AI Chip Design appeared first on From Silicon To Software....
Jan 12, 2022
In addition to sporting a powerful processor and supporting Bluetooth wireless communications, Seeed's XIAO BLE Sense also boasts a microphone and a 6DOF IMU....

featured video

Synopsys & Samtec: Successful 112G PAM-4 System Interoperability

Sponsored by Synopsys

This Supercomputing Conference demo shows a seamless interoperability between Synopsys' DesignWare 112G Ethernet PHY IP and Samtec's NovaRay IO and cable assembly. The demo shows excellent performance, BER at 1e-08 and total insertion loss of 37dB. Synopsys and Samtec are enabling the industry with a complete 112G PAM-4 system, which is essential for high-performance computing.

Click here for more information about DesignWare Ethernet IP Solutions

featured paper

Building Automation and Control Systems (BACS)

Sponsored by Analog Devices

Analog Devices' industrial communication products provide building automation engineers with a broad range of Analog IO, Digital IO, Isolation, and communication interfaces that combine low power, robust performance, and improved diagnostics in the smallest possible form factors.

Click here to read more

featured chalk talk

How Trinamic's Stepper Motor Technologies Improve Your Application

Sponsored by Mouser Electronics and Analog Devices

Stepper motor control has come a long way in the past few years. New techniques can give greater control, smoother operation, greater torque, and better efficiency. In this episode of Chalk Talk, Amelia Dalton chats with Lars Jaskulski about Trinamic stepper solutions and how to take advantage of micro stepping, load measurement, and more.

Click here for more information about Trinamic TMCM-6110 6-Axis Stepper Motor Driver Board