editor's blog
Subscribe Now

Software Validation News

LDRA and PRQA both had news at ESC last week. As a reminder, LDRA focuses on the traceability and certification of software, especially software targeted for safety-critical and secure applications. PRQA, on the other hand, prides itself in its deep, detailed code analysis, looking for potential bugs or other problems.

LDRA announced the ability to provide traceability from requirements all the way to object code. It’s that last mile to object code that’s new. The idea is to be able to document that all of the executable code can be traced to a requirement; that is, there’s no bonus flight simulator buried in your medical app for the nurses to play with. It’s also nice to go the other direction: show that every requirement has been met.

They also announced implementation of the Homeland Security secure programming guidelines.

Meanwhile, PRQA announced data flow analysis using a satisfiability modulo theorem solver (“sat solver”) from SRI that apparently won an annual sat solver competition two years ago (apparently, in declaring victory, they sat out last year’s bout). While the use of sat solvers in software analysis is by no means new, PRQA claims that it’s never been used for the kind of deep analysis they do. Others tend to try to abstract elements of the program so the entire program can be analyzed as a whole; such analysis would miss much of the detail PRQA finds. Conversely, PRQA, in rooting out the low-level details, might miss some higher-level issues; that’s not their focus.

More details in their object code traceability, HLS certification, and dataflow analysis releases…

Leave a Reply

featured blogs
Jun 22, 2021
Have you ever been in a situation where the run has started and you realize that you needed to add two more workers, or drop a couple of them? In such cases, you wait for the run to complete, make... [[ Click on the title to access the full blog on the Cadence Community site...
Jun 21, 2021
By James Paris Last Saturday was my son's birthday and we had many things to… The post Time is money'¦so why waste it on bad data? appeared first on Design with Calibre....
Jun 17, 2021
Learn how cloud-based SoC design and functional verification systems such as ZeBu Cloud accelerate networking SoC readiness across both hardware & software. The post The Quest for the Most Advanced Networking SoC: Achieving Breakthrough Verification Efficiency with Clou...
Jun 17, 2021
In today’s blog episode, we would like to introduce our newest White Paper: “System and Component qualifications of VPX solutions, Create a novel, low-cost, easy to build, high reliability test platform for VPX modules“. Over the past year, Samtec has worked...

featured video

Reduce Analog and Mixed-Signal Design Risk with a Unified Design and Simulation Solution

Sponsored by Cadence Design Systems

Learn how you can reduce your cost and risk with the Virtuoso and Spectre unified analog and mixed-signal design and simulation solution, offering accuracy, capacity, and high performance.

Click here for more information about Spectre FX Simulator

featured paper

An FPGA-Based Solution for a Graph Neural Network Accelerator

Sponsored by Achronix

Graph Neural Networks (GNN) drive high demand for compute and memory performance and a software only based implementation of a GNN does not meet performance targets. As a result, there is an urgent need for hardware-based GNN acceleration. While traditional convolutional neural network (CNN) hardware acceleration has many solutions, the hardware acceleration of GNN has not been fully discussed and researched. This white paper reviews the latest GNN algorithms, the current status of acceleration technology research, and discusses FPGA-based GNN acceleration technology.

Click to read more

featured chalk talk

Accelerating Physical Verification Productivity Part Two

Sponsored by Synopsys

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Click here for more information about Physical Verification using IC Validator