editor's blog
Subscribe Now

Get Wreal

When analog design discussions turn to simulation, especially when they involve Cadence, one inevitably comes up against the unfortunately-named concept of the “wreal” type. I say “unfortunately” because, pronounced with standard English rules, it’s pronounced “real,” providing no audible distinction from the “real” type. So it’s typically pronounced “double-you-real.” (Or occasionally you’ll hear “wuh-real.”) Yeah, unfortunate.

It’s also difficult to find information on exactly what it is and the context driving its use. It’s easy to learn that it can make some simulation faster, but, somehow, from there you end up diving way down into the nitty gritty of differences between the Verilog-AMS version and Cadence’s version and specific problems being discussed in forums and… well… let’s just try to back up a bit. I was able to talk to Mladen Nizic, a Cadence engineering director, in an attempt to articulate a big-picture statement of the role of the wreal.

First some background. Analog and digital simulators fundamentally work differently. An analog simulator attempts to calculate the state or operating point of a complete circuit. It’s a static, holistic, matrix calculation that is then repeated over very small time increments in an attempt to model continuous time. At any given time, the voltage and current are known for any node.

By contrast, digital simulators model the flow of signals from stimulus to response, driven by events, and they assume the discrete time behavior afforded by a clock. There are no voltages or currents, only 1s and 0s. (And Xs.)

Wreal signals help to bridge the divide between pure analog simulation and full-chip analog/mixed-signal (AMS) simulation. This is necessary for two reasons: AMS simulation must account for the preponderance of digital content, and the size of these chips means that higher simulation performance is needed than would be remotely possible if you tried to simulate the entire chip at an analog level.

With a wreal signal, you can take a voltage or current (but not both) between modules of the full chip. It can operate in a signal-flow fashion, behaving more like a digital signal. This allows it to play nicely in the digital simulation paradigm.

Cadence has made some extensions to the standard wreal:

–          You can typecast signals to/from wreal

–          You can have arrays of wreals

–          You can have multiple drivers on a wreal signal (and the tool will resolve the correct voltage or current)

You still need to do your full analog simulation to make sure your analog module is working properly, but you can now integrate the analog block into your full-chip simulation to make sure that it plays nicely with everything else.

 

When discussions of analog simulation [B1] arise, especially when they involve Cadence, one inevitably comes up against the unfortunately-named concept of the “wreal” type. I say “unfortunately” because, pronounced with standard English rules, it’s pronounced “real,” providing no audible distinction from the “real” type. So it’s typically pronounced “double-you-real.” (Or occasionally you’ll hear “wuh-real.”) Yeah, unfortunate.

It’s also difficult to find information on exactly what it is and the context driving its use. It’s easy to learn that it can make some simulation faster, but, somehow, from there you end up diving way down into the nitty gritty of differences between the Verilog-AMS version and Cadence’s version and specific problems being discussed in forums and… well… let’s just try to back up a bit. I was able to talk to Mladen Nizic, a Cadence engineering director, in an attempt to articulate a big-picture statement of the role of the wreal.

First some background. Analog and digital simulators fundamentally work differently. An analog simulator attempts to calculate the state or operating point of a complete circuit. It’s a static, holistic, matrix calculation that is then repeated over very small time increments in an attempt to model continuous time. At any given time, the voltage and current are known for any node.

By contrast, digital simulators model the flow of signals from stimulus to response, driven by events, and they assume the discrete time behavior afforded by a clock. There are no voltages or currents, only 1s and 0s. (And Xs.)

Wreal signals help to bridge the divide between pure analog simulation and full-chip analog/mixed-signal (AMS) simulation. This is necessary for two reasons: AMS simulation must account for the preponderance of digital content, and the size of these chips means that higher simulation performance is needed than would be remotely possible if you tried to simulate the entire chip at an analog level.

With a wreal signal, you can take a voltage or current (but not both) between modules of the full chip. It can operate in a signal-flow fashion, behaving more like a digital signal. This allows it to play nicely in the digital simulation paradigm.

Cadence has made some extensions to the standard wreal:

          You can typecast signals to/from wreal

          You can have arrays of wreals

          You can have multiple drivers on a wreal signal (and the tool will resolve the correct voltage or current)

You still need to do your full analog simulation to make sure your analog module is working properly, but you can now integrate the analog block into your full-chip simulation to make sure that it plays nicely with everything else.


 [B1]Link to surrender article

Leave a Reply

featured blogs
Nov 23, 2022
The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creat...
Nov 22, 2022
Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs. The post What's Driving the World's First Analog and Mixed-Signal Emulation Technology? appeared first on From Silicon To So...
Nov 21, 2022
By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

Maximizing Power Savings During Chip Implementation with Dynamic Refresh of Vectors

Sponsored by Synopsys

Drive power optimization with actual workloads and continually refresh vectors at each step of chip implementation for maximum power savings.

Learn more about Energy-Efficient SoC Solutions

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Sensor Technologies Here to Stay: Post-pandemic

Sponsored by Infineon

Today sensor technology has become integral to our everyday lives. And in the future, sensor technology will mean even more than it does today. In this episode of Chalk Talk, Amelia Dalton chats with David Jones from Infineon about the future of sensor technologies and how they are going to impact our lives in the post-pandemic world. They investigate how miniaturization, built-in antennas in-package and the evolution of radar technology have helped usher in a whole new era of sensing technologies and how all of this and more will help us live healthier and happier lives.

Click here for more information about Infineon's sensor technology portfolio