editor's blog
Subscribe Now

Get Wreal

When analog design discussions turn to simulation, especially when they involve Cadence, one inevitably comes up against the unfortunately-named concept of the “wreal” type. I say “unfortunately” because, pronounced with standard English rules, it’s pronounced “real,” providing no audible distinction from the “real” type. So it’s typically pronounced “double-you-real.” (Or occasionally you’ll hear “wuh-real.”) Yeah, unfortunate.

It’s also difficult to find information on exactly what it is and the context driving its use. It’s easy to learn that it can make some simulation faster, but, somehow, from there you end up diving way down into the nitty gritty of differences between the Verilog-AMS version and Cadence’s version and specific problems being discussed in forums and… well… let’s just try to back up a bit. I was able to talk to Mladen Nizic, a Cadence engineering director, in an attempt to articulate a big-picture statement of the role of the wreal.

First some background. Analog and digital simulators fundamentally work differently. An analog simulator attempts to calculate the state or operating point of a complete circuit. It’s a static, holistic, matrix calculation that is then repeated over very small time increments in an attempt to model continuous time. At any given time, the voltage and current are known for any node.

By contrast, digital simulators model the flow of signals from stimulus to response, driven by events, and they assume the discrete time behavior afforded by a clock. There are no voltages or currents, only 1s and 0s. (And Xs.)

Wreal signals help to bridge the divide between pure analog simulation and full-chip analog/mixed-signal (AMS) simulation. This is necessary for two reasons: AMS simulation must account for the preponderance of digital content, and the size of these chips means that higher simulation performance is needed than would be remotely possible if you tried to simulate the entire chip at an analog level.

With a wreal signal, you can take a voltage or current (but not both) between modules of the full chip. It can operate in a signal-flow fashion, behaving more like a digital signal. This allows it to play nicely in the digital simulation paradigm.

Cadence has made some extensions to the standard wreal:

–          You can typecast signals to/from wreal

–          You can have arrays of wreals

–          You can have multiple drivers on a wreal signal (and the tool will resolve the correct voltage or current)

You still need to do your full analog simulation to make sure your analog module is working properly, but you can now integrate the analog block into your full-chip simulation to make sure that it plays nicely with everything else.

 

When discussions of analog simulation [B1] arise, especially when they involve Cadence, one inevitably comes up against the unfortunately-named concept of the “wreal” type. I say “unfortunately” because, pronounced with standard English rules, it’s pronounced “real,” providing no audible distinction from the “real” type. So it’s typically pronounced “double-you-real.” (Or occasionally you’ll hear “wuh-real.”) Yeah, unfortunate.

It’s also difficult to find information on exactly what it is and the context driving its use. It’s easy to learn that it can make some simulation faster, but, somehow, from there you end up diving way down into the nitty gritty of differences between the Verilog-AMS version and Cadence’s version and specific problems being discussed in forums and… well… let’s just try to back up a bit. I was able to talk to Mladen Nizic, a Cadence engineering director, in an attempt to articulate a big-picture statement of the role of the wreal.

First some background. Analog and digital simulators fundamentally work differently. An analog simulator attempts to calculate the state or operating point of a complete circuit. It’s a static, holistic, matrix calculation that is then repeated over very small time increments in an attempt to model continuous time. At any given time, the voltage and current are known for any node.

By contrast, digital simulators model the flow of signals from stimulus to response, driven by events, and they assume the discrete time behavior afforded by a clock. There are no voltages or currents, only 1s and 0s. (And Xs.)

Wreal signals help to bridge the divide between pure analog simulation and full-chip analog/mixed-signal (AMS) simulation. This is necessary for two reasons: AMS simulation must account for the preponderance of digital content, and the size of these chips means that higher simulation performance is needed than would be remotely possible if you tried to simulate the entire chip at an analog level.

With a wreal signal, you can take a voltage or current (but not both) between modules of the full chip. It can operate in a signal-flow fashion, behaving more like a digital signal. This allows it to play nicely in the digital simulation paradigm.

Cadence has made some extensions to the standard wreal:

          You can typecast signals to/from wreal

          You can have arrays of wreals

          You can have multiple drivers on a wreal signal (and the tool will resolve the correct voltage or current)

You still need to do your full analog simulation to make sure your analog module is working properly, but you can now integrate the analog block into your full-chip simulation to make sure that it plays nicely with everything else.


 [B1]Link to surrender article

Leave a Reply

featured blogs
Jun 13, 2024
I've just been introduced to the DuoFlex 4K Dual-Screen Display from HalmaPixel, and now I'm drooling with desire all over my keyboard....

featured video

Unleashing Limitless AI Possibilities with FPGAs

Sponsored by Intel

Industry experts discuss real-world AI solutions based on Programmable Logic, or FPGAs. The panel talks about a new approach called FPGAi, what it is and how it will revolutionize how innovators design AI applications.

Click here to learn more about Leading the New Era of FPGAi

featured paper

DNA of a Modern Mid-Range FPGA

Sponsored by Intel

While it is tempting to classify FPGAs simply based on logic capacity, modern FPGAs are alterable systems on chips with a wide variety of features and resources. In this blog we look closer at requirements of the mid-range segment of the FPGA industry.

Click here to read DNA of a Modern Mid-Range FPGA - Intel Community

featured chalk talk

Autonomous Robotics Connectivity Solutions
Sponsored by Mouser Electronics and Samtec
Connectivity solutions for autonomous robotic applications need to include a variety of orientations, stack heights, and contact systems. In this episode of Chalk Talk, Amelia Dalton and Matthew Burns from Samtec explore trends in autonomous robotic connectivity solutions and the benefits that Samtec interconnect solutions bring to these applications.
Jan 22, 2024
21,332 views