Sitting through iSQED presentations on single-event-upset-tolerant circuits, I couldn’t help but notice the recurrent C2MOS moniker being tossed about. It was unclear to me whether it was stimulating some old, moldy memory or if that was just my imagination.
Some subsequent poking around to learn more proved harder than I expected. The term is tossed out here and there, but it was actually really difficult to confirm what it stands for: Clocked CMOS.
And then I saw a reference to it from 1973: this clearly isn’t new technology. So it is entirely possible that we skimmed through it in my college logic class as one of many digital curiosities.
But it’s apparently being taken seriously today: activity is up since the mid-2000s. The benefit appears to be that latches and flip-flops are much less sensitive to clock overlap issues and race conditions (although they don’t eliminate the normal setup requirements between data and clock.)
A C2MOS latch is really simple. Picture an inverter, which is a two-transistor stack, a P over an N. Now insert another complementary pair of transistors into this stack, so now you have two Ps over two Ns. You drive the added N by CLK and the added P by /CLK. The clock inverter pair isolates the effects of changes to the data from the output. So you set up new data, and only when you toggle the clock are the new values presented to the output. (Some versions show a small keeper on the output since, after the clock reverts back, this is a high-impedance node.)
With this setup, once the new latch data is in place, it doesn’t matter how well timed the CLK and /CLK lines are: the data P and N transistors guarantee the stack to be in a high-impedance state, so you won’t get any crowbar current. (You can get into trouble if the CLK rise and fall times are two slow, but that’s easy to fix. Easy for me to say…)
It is presumably this robustness that is bringing the design style back into favor in circuits that have to be tolerant of an inhospitable welcome.