editor's blog
Subscribe Now

Going Up

It’s always helpful when complex new technological ideas can be related to everyday concepts. So when I heard about “test elevators,” proposed by imec, for 3D IC DFT, naturally my interest was piqued. It’s an intriguing image, conjuring up thoughts of complex ways of managing tests on multiple dice.

Alas, as it turns out, there’s really no new technology associated with this: it’s simply the idea of allocating some TSVs for testing. Which is the same as allocating wires for test signals on a 2D chip.

So if the vertical ones are test elevators, then the plain-old wires we’ve been using should perhaps be called “test sidewalks” or “test freeways.”

At the end of the day, it’s just a metal connection.

Leave a Reply

featured blogs
Feb 20, 2019
'€œTime to design completion'€ is almost always the primary metric and the cause for the most angst within a design team. Your customers demand that a package design is completed as quickly as possible... [[ Click on the title to access the full blog on the Cadence Comm...
Feb 19, 2019
“So, what really is 5G?”. That may be a question some folks are asking themselves. Why? No one has really heard of 5G yet. Right? Insert rolling eye emoji here. In case someone lives under a rock, “5G” refers to the next-gen cellular standard that will...
Feb 15, 2019
This year at DVCon US, Mentor is going to add some sizzle to our booth (#1005) during the exhibit hours. In addition to our stellar demo staff who are always available to answer questions and show you the latest capabilities of our tools, we’re also going to be hosting ...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...