editor's blog
Subscribe Now

Going Up

It’s always helpful when complex new technological ideas can be related to everyday concepts. So when I heard about “test elevators,” proposed by imec, for 3D IC DFT, naturally my interest was piqued. It’s an intriguing image, conjuring up thoughts of complex ways of managing tests on multiple dice.

Alas, as it turns out, there’s really no new technology associated with this: it’s simply the idea of allocating some TSVs for testing. Which is the same as allocating wires for test signals on a 2D chip.

So if the vertical ones are test elevators, then the plain-old wires we’ve been using should perhaps be called “test sidewalks” or “test freeways.”

At the end of the day, it’s just a metal connection.

Leave a Reply

featured blogs
Apr 24, 2019
In this week's Whiteboard Wednesdays video, Industry expert Rohit Kapur introduces the basic concepts of digital IC scan compression. Topics explained include the impacts of test application time... [[ Click on the title to access the full blog on the Cadence Community ...
Apr 23, 2019
Samtec Bulls Eye® test point systems are ideal for high-performance test applications because of their compression interfaces, small footprint, and high cycle count capabilities. Bulls Eye is now available in 50 GHz and 20 GHz designs, with a system up to 70 GHz in developme...
Apr 23, 2019
Move over, Information Age'€”the Autonomous Age is on its way. In the autonomous age, information is not just copious and accessible, it is integrated into our daily lives to automatically augment human capabilities. In the autonomous age, we expect technology to comprehend...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...