editor's blog
Subscribe Now

Quicker LTE Validation

Each new communications protocol adds to the complexity of its predecessor, and the 3GPP-LTE cellular standard is no exception. According to Synopsys, there are more than a thousand tests specified in the standard to ensure compliance.

And it’s actually twice that bad: before you cut a chip, you need to verify the design against those tests. Then, when the chip comes out, you need to verify the actual silicon against the same tests.

For this reason, Synopsys – maker of pre-silicon design tools – and Rhode & Schwarz – maker of post-silicon, real, you-can-put-your-hands-on-it lab equipment – have paired up to make the whole process more efficient.

Both Synopsys and Rhode & Schwarz have LTE IP: the former in the form of simulation models in their SPW/System Studio tool; the latter in the form of pre-configured IP for their signal generators. Well, almost pre-configured: there are in the range of 60 to 100 parameters that need to be set for any given test.

So now you can import those parameters from the Synopsys tools both to speed things up and to ensure that the settings are consistent between simulation and test. That means less time debugging the test setup.

In addition, users can now take simulation results and compare them against the actual silicon measurements, giving easier access to any discrepancies and shortening silicon validation. This feature also allowed Synopsys to validate its own LTE simulation libraries against real silicon.

More details in their release

Leave a Reply

featured blogs
Mar 27, 2023
Spectre EMIR, the simulation engine inside Voltus-XFi, provides the IR drop and EM current analyses. In reviews of the reported customer problems, it turns out that many Spectre EMIR problems can be avoided by proper preparation and setup. The most common problem Spectre EMIR...
Mar 23, 2023
Explore AI chip architecture and learn how AI's requirements and applications shape AI optimized hardware design across processors, memory chips, and more. The post Why AI Requires a New Chip Architecture appeared first on New Horizons for Chip Design....
Mar 10, 2023
A proven guide to enable project managers to successfully take over ongoing projects and get the work done!...

featured video

First CXL 2.0 IP Interoperability Demo with Compliance Tests

Sponsored by Synopsys

In this video, Sr. R&D Engineer Rehan Iqbal, will guide you through Synopsys CXL IP passing compliance tests and demonstrating our seamless interoperability with Teladyne LeCroy Z516 Exerciser. This first-of-its-kind interoperability demo is a testament to Synopsys' commitment to delivering reliable IP solutions.

Learn more about Synopsys CXL here

featured chalk talk

ActiveCiPS™: Configurable Intelligent Power Management Solutions
Sponsored by Mouser Electronics and Qorvo
Programmable power management can not only help us manage our power systems but it can also have size, weight, and cost benefits as well. In this episode of Chalk Talk, Amelia Dalton chats with Yael Coleman from Qorvo about the system-wide benefits of configurable power management solutions. They investigate the programmable features of the ActiveCips configurable intelligent power management solutions and review how these solutions can help you balance weight, size, power and cost in your next design.
Jul 19, 2022
30,826 views