editor's blog
Subscribe Now

Quicker LTE Validation

Each new communications protocol adds to the complexity of its predecessor, and the 3GPP-LTE cellular standard is no exception. According to Synopsys, there are more than a thousand tests specified in the standard to ensure compliance.

And it’s actually twice that bad: before you cut a chip, you need to verify the design against those tests. Then, when the chip comes out, you need to verify the actual silicon against the same tests.

For this reason, Synopsys – maker of pre-silicon design tools – and Rhode & Schwarz – maker of post-silicon, real, you-can-put-your-hands-on-it lab equipment – have paired up to make the whole process more efficient.

Both Synopsys and Rhode & Schwarz have LTE IP: the former in the form of simulation models in their SPW/System Studio tool; the latter in the form of pre-configured IP for their signal generators. Well, almost pre-configured: there are in the range of 60 to 100 parameters that need to be set for any given test.

So now you can import those parameters from the Synopsys tools both to speed things up and to ensure that the settings are consistent between simulation and test. That means less time debugging the test setup.

In addition, users can now take simulation results and compare them against the actual silicon measurements, giving easier access to any discrepancies and shortening silicon validation. This feature also allowed Synopsys to validate its own LTE simulation libraries against real silicon.

More details in their release

Leave a Reply

featured blogs
Apr 4, 2025
Gravitrams usually employ a chain or screw lift to hoist their balls from the bottom to the top, but why not use a robot?...

featured paper

How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability

Sponsored by Siemens Digital Industries Software

Through real-world examples from Intel and Google, we highlight how Calibre’s DesignEnhancer maximizes layout modifications while ensuring DRC compliance.

Click here for more information

featured chalk talk

Accelerating Time to Fault Campaign Success with Siemens EDA
In this episode of Chalk Talk, Ann Keffer and Robert Serphillips from Siemens and Amelia Dalton explore how the Siemens EDA functional safety platform can guide your team through the complete ISO 26262 lifecycle. They also examine the benefits that the Veloce Fault App brings to automotive IC designs and how you can take advantage of the full suite of functional tools from Siemens EDA for your next automotive IC design.
Apr 14, 2025
1,226 views