editor's blog
Subscribe Now

FLASH Gets Even Smaller

It feels, at first blush, like the conventional wisdom about floating gate cells not having a future at tiny dimensions may have to go the way lots of conventional wisdom goes. On the heels of Kilopass’s 40-nm MTP announcement, Micron and Intel announced NAND FLASH at as low as 20 nm.

So much for not scalable below 90 nm.

The issue here is too much tunneling when the oxides get too thin. It wasn’t supposed to work with oxides this thin. So… was that wrong?

Well, yes and no. According to Micron, “as oxides have gotten thinner, we have had to come up with more complex oxide and dielectric materials.” And they’re not saying more than that. Presumably that means that it’s not trivial and therefore it’s secret. Or maybe it is trivial; even more reason to keep it secret.

Of course, if electrons were tunneling without permission, the result would be decreased data retention. Such leakage gets worse with repeated programming assaults, so the net net of that is that data retention on these memories stays as it always has, but the endurance goes down.

But Micron says they’re playing with one more variable: density. They’re talking about “data retention per byte” as a metric, which is increasing because density is going up faster than endurance is coming down. It sounds from this like they can use the extra density as redundancy to swap out as cells wear out.

So does this mean that those saying you can’t go below 90 nm are being less than honest? Does that mean the conventional wisdom is wrong? Actually, no; there’s one more distinction: as suggested above, it takes special processing to do this. So you can’t simply make this kind of memory cell using a standard logic process. That’s where things break down. So Kilopass is selling IP for integration on chips with other logic (so-called Logic NVM); Micron and Intel aren’t.

More info in their press release

Leave a Reply

featured blogs
Jun 12, 2025
We truly do live in a world that would have been considered to be a far-flung science fiction future only a few short decades ago...

featured paper

Shift Left with Calibre Pattern Matching: Trust in design practices but verify early and frequently

Sponsored by Siemens Digital Industries Software

As integrated circuit (IC) designs become increasingly complex, early-stage verification is crucial to ensure productivity and quality in design processes. The "shift left" verification approach, enabled by Siemens’ Calibre nmPlatform, helps IC design teams to identify and resolve critical issues much earlier in the design cycle.

Click to read more

featured chalk talk

Accelerating Tapeouts with Synopsys Cloud and AI
Sponsored by Synopsys
In this episode of Chalk Talk, Amelia Dalton and Vikram Bhatia from Synopsys explore how you can accelerate your next tapeout with Synopsys Cloud and AI. They also discuss new enhancements and customer use cases that leverage AI with hybrid cloud deployment scenarios, and how this platform can help CAD managers and engineers reduce licensing overheads and seamlessly run complex EDA design flows through Synopsys Cloud.
Jul 8, 2024
78,747 views