It feels, at first blush, like the conventional wisdom about floating gate cells not having a future at tiny dimensions may have to go the way lots of conventional wisdom goes. On the heels of Kilopass’s 40-nm MTP announcement, Micron and Intel announced NAND FLASH at as low as 20 nm.
So much for not scalable below 90 nm.
The issue here is too much tunneling when the oxides get too thin. It wasn’t supposed to work with oxides this thin. So… was that wrong?
Well, yes and no. According to Micron, “as oxides have gotten thinner, we have had to come up with more complex oxide and dielectric materials.” And they’re not saying more than that. Presumably that means that it’s not trivial and therefore it’s secret. Or maybe it is trivial; even more reason to keep it secret.
Of course, if electrons were tunneling without permission, the result would be decreased data retention. Such leakage gets worse with repeated programming assaults, so the net net of that is that data retention on these memories stays as it always has, but the endurance goes down.
But Micron says they’re playing with one more variable: density. They’re talking about “data retention per byte” as a metric, which is increasing because density is going up faster than endurance is coming down. It sounds from this like they can use the extra density as redundancy to swap out as cells wear out.
So does this mean that those saying you can’t go below 90 nm are being less than honest? Does that mean the conventional wisdom is wrong? Actually, no; there’s one more distinction: as suggested above, it takes special processing to do this. So you can’t simply make this kind of memory cell using a standard logic process. That’s where things break down. So Kilopass is selling IP for integration on chips with other logic (so-called Logic NVM); Micron and Intel aren’t.
More info in their press release…