Meet UVVM: The World’s #1 VHDL Verification Methodology
I’m happy (albeit puzzled) to tell you that things seem to be getting better with respect to verifying FPGA, ASIC, and system-on-chip (SoC) designs. The reason I say this is that the last time I turned my attention to this arena, people were saying that the design and verification phases of a complex device consumed 30% and 70% of the total development time, respectively. By comparison, someone recently informed me that these numbers are now more like 50% and 50%, which means either we’ve become better at doing verification or worse at doing design.
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