I Just Created my First AI/ML App! (Part 1)

I’m currently scampering around my office with a great big beaming smile plastered all over my face because I just created my very first artificial intelligence (AI) / machine learning (ML) application… and it works!

When people hear the terms AI and ML, very often their knee-jerk reaction is to think about machine vision and things like object detection and … Read More → "I Just Created my First AI/ML App! (Part 1)"

Interview: RISC-V CTO Mark Himelstein

“One man’s constant is another man’s variable.” – programmers’ wisdom

Most engineering firms have a CTO. The Chief Technical Officer sets the technical direction, guides the research, gives the engineers their marching orders, and in between lectures strokes his beard and thinks deeply technical thoughts. 

But what does the CTO of … Read More → "Interview: RISC-V CTO Mark Himelstein"

SSDs Aren’t Just Faster Hard Disks

“But it’s all right. I’m Jumpin’ Jack Flash. It’s a gas, gas, gas.” – Keith Richards/Mick Jagger

A new hard disk controller. Ho-hum, yawn. But this one says it improves performance tenfold. Huh? How is that possible? And that it increases price/performance by 90%. This also seemed implausible. Time to dig into these nonsense claims.  </ … Read More → "SSDs Aren’t Just Faster Hard Disks"

Advancing into FinFET

In this week’s podcast, we are talking about embedded in-chip monitoring and lifecycle chip design challenges with Stephen Crosher and Oliver King from Moortec. We also take a closer look at a new breakthrough in data storage technology and why a team of researchers from Stanford, UC Berkeley, and Texas A&M believe that tiny slices of tungsten ditelluride may just hold the key to the evolution … Read More → "Advancing into FinFET"

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Featured Chalk Talk

TensorFlow to RTL with High-Level Synthesis

Sponsored by Cadence Design Systems

Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.

More information

Featured Paper

Improving Performance in High-Voltage Systems With Zero-Drift Hall-Effect Current Sensing

Sponsored by Texas Instruments

Learn how major industry trends are driving demands for isolated current sensing, and how new zero-drift Hall-effect current sensors can improve isolation and measurement drift while simplifying the design process.

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featured video

Product Update: High-Performance DesignWare Memory Interface IP

Sponsored by Synopsys

Get the latest update on Synopsys' DesignWare Memory Interface IP for DDR5, LPDDR5, and HBM2/2E and how you can enable your DRAMs with the highest-performance, lowest-power, and lowest-area IP solution.

Click here to learn more about Synopsys' DesignWare Memory Interface IP for DDR5, LPDDR5, and HBM2/2E

discussion
Posted on Aug 6 at 10:55am by charles.petras@gmail.com
How about a For Dummies on using the GPT-2 and/or GPT-3 ?
Posted on Aug 6 at 5:36am by DavidPatterson
I'm happy to inform you that I'm perfectly happy with RISC-V, and I am not working on RISC-VI. I'm currently working on a video to celebrate the 10th birthday of RISC-V, which started May 18, 2010. We're interviewing people involved over it's first decade, and asking them to talk about the impact ...
Posted on Aug 3 at 9:41pm by varase
AFAIK, Rosetta 2's main mode of operation is to transcode Intel binaries to Apple silicon binaries on install, storing the AArch64 code in the same manner as a Universal 2 compile will do (whether that's in a separate resource or file I don't know). Dynamically loaded code is treated differently, though ...
Posted on Aug 3 at 9:41am by Jim Turley
Nice. It's surprising (to me, anyway) how many digital problems can be traced to bad AC power.
Posted on Jul 30 at 12:01pm by acantle
Great article Kevin, nicely covering all the bases here. It defines the exact challenge that my new venture, Nallasway, is hoping to tackle. We need a first principles grassroots approach to this, to truly benefit from this once in a lifetime shift in our industry.
Posted on Jul 30 at 8:37am by JayN
yes, I agree on the heterogeneous programming. It will be interesting to see if oneAPI succeeds. The programmer still needs to be aware of the target device to get the best optimization. However, there was also an article yesterday on "Machine-Programming Code Similarity System", using AI to write code, with ...
Posted on Jul 29 at 7:02am by muldrow
Years ago I was encountering an intermittent reset on a new circuit board that would only occur once every couple of days. Instrumenting on the board indicated a noise burst on the power line that only went off every 2 or 3 days. I set up a scope probe on the AC ...
Posted on Jul 28 at 2:19pm by fpgareader
But how do we trust the 3rd party security company - over time? But DIY is heavy as Jim said: see this ETSI Security doc: https://bit.ly/3f8xExZ A Good Read for embedded guys so you’ll be ready when your bosses panic over their IoT device liabilities.
Posted on Jul 28 at 8:26am by Max Maxfield
Now you are making me feel guilty -- but you are assuming the resonant frequency is in the ultrasonic -- suppose it was < 20 Hz...
Posted on Jul 28 at 8:24am by Max Maxfield
Hi Ivan -- They showed me the frequency response curves -- in fact I have them here in my office -- I'll show them to you the next time you drop round for a cup of tea :-)
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[From the last episode: We looked at the notion of sparsity and how it helps with the math.] We saw before that there are three main elements in a CNN: the convolution, the pooling, and the activation . Today we focus on activation . I'€™ll start by saying that the uses of ...
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