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The New, New Intel Unleashes a Technology Barrage

“3D XPoint is nothing short of a miracle.” – Alber Ilkbahar

Intel just celebrated the start of its 50th year. For those who were not following closely in 1968, Robert Noyce and Gordon Moore founded Intel Corporation on July 18 of that year. That’s a year after the Summer of Love and … Read More → "The New, New Intel Unleashes a Technology Barrage"

A More Reliable MRAM Mechanism

The search continues for the perfect memory cell that will replace SRAM, DRAM, and flash memory cells with better performance, power, and reliability characteristics than any of those three. While we’ve seen a number of contenders, there isn’t really any cell that is optimal for all three. Typically, cells will target either SRAM (and maybe DRAM) for in-operation memory, or flash for long-term storage.Read More → "A More Reliable MRAM Mechanism"

Programmability’s Promise

Need programmability? Step right up my friends. In this week’s Fish Fry, we are investigating some of the newest and coolest applications using programmable technology today. Ted Marena (Microsemi) demonstrates how we can use PolarFire FPGAs in a machine-learning application and how this PolarFire FPGA-based board can also facilitate Linux and RISC-V development. Sunder Parameswaran (Falcon Computing) also joins us to discuss some really cool applications for FPGA … Read More → "Programmability’s Promise"

Re-interpreting Moore’s Law

For two or three decades, there has been raging debate about the longevity and relevance of Moore’s Law. Is it dead? Has it changed? Is it slowly fizzling out? Was it a law or just a projection? Is it really about transistor density only, or something more conceptual? Did Moore really say “doubles every two years” or was it more like 18 months? Was Moore’s … Read More → "Re-interpreting Moore’s Law"

Virtual Verification Smorgasbord

Pull up a chair. Take a taste. Come join us. Life is so endlessly delicious. — Ruth Reichl

Are you ready for a virtual buffet of verification goodness? I hope so. In this week’s Fish Fry, we’re gobbling down as much verification as we possibly can fit on our podcastin’ plate. First up, Anupam Bakshi (Agnisys) joins us to dish on register specification, automatic … Read More → "Virtual Verification Smorgasbord"

Sigrity Elevates 3D

Signal integrity (SI) is the bane of most system designers. Getting those signals to pass intact through all the twists and turns of your design can be a maddening experience. But modern signal integrity design and analysis is the enabling soul of most of today’s high-performance systems. Cadence’s Sigrity tools are an industry leader in the signal and power integrity game, and the recently … Read More → "Sigrity Elevates 3D"

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featured blogs
Aug 15, 2018
The world recognizes the American healthcare system for its innovation in precision medicine, surgical techniques, medical devices, and drug development. But they'€™ve been slow to adopt 21st century t...
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Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...
chalk talks
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"