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Q&A with Xilinx President and CEO Victor Peng

“Strategy is about setting yourself apart from the competition” – Michael Porter, Harvard Business School

Earlier this month, Xilinx announced the 7nm Versal ACAP series of advanced programmable ICs along with a new board-level hardware accelerator for data centers called Alveo. Xilinx President and CEO  Victor Peng announced these products during his keynote on October 2 at the Xilinx Developers Forum (XDF) held in … Read More → "Q&A with Xilinx President and CEO Victor Peng"

Why does Xilinx say That its New 7nm Versal “ACAP” isn’t an FPGA?

Xilinx has been performing a slow reveal of its new ACAP (adaptive compute acceleration platform) architecture for many months, and the company unveiled much more—including the new “Versal” family name and six (!) new, multi-member series (aka families) of 7nm ACAP devices—at its October 1 Xilinx Developers Forum (XDF), held in San Jose, California. (The company says that “Versal” is a contraction of the words “versatile” … Read More → "Why does Xilinx say That its New 7nm Versal “ACAP” isn’t an FPGA?"

Wally Rhines Talks About the Future of PCB and System Design

“Your future is whatever you make it. So make it a good one.” – Doc Brown

Wally Rhines is like the Energizer Bunny of the EDA industry. He’s a favorite and frequent on-stage presenter at industry events. Perhaps that’s because he’s an all-around nice guy, but, more likely, it’s because his presentations are so darn interesting. Latest case in … Read More → "Wally Rhines Talks About the Future of PCB and System Design"

Moore’s Law Only Ends Once

I hope you have your seatbelt low and tight across your waist my friends, because we are flying high into cloud-based design in this week’s episode of Fish Fry! With templates, code, tools, fabs and processes in the cloud cargo hold, Naveed Sherwani (CEO – SiFive), Yunsup Lee (CTO/Founder – SiFive), and I are headed straight into the next generation of silicon design. Also this week, … Read More → "Moore’s Law Only Ends Once"

October 19, 2018
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featured blogs
Oct 19, 2018
过孔转换对信号布线来说十分常见。在高速设计中过孔转换是造成PCB互连中信号衰减的主要原因。而且高é...
Oct 19, 2018
Any engineer who has designed an IC-based solution likely used some sort of HW development tool. Semiconductor manufacturers have a long history of providing engineers with the HW tools needed to test their silicon. Evaluation platforms, like the Xilinx® Zynq UltraScale+ ...
Oct 16, 2018
  IC Insights has just published the September Update to The 2018 McClean Report, and one figure (reproduced below) puts yet another nail into the coffin for poor old Moore'€™s Law. Now please take care. There'€™s a vertical line between the 200mm wafers on the left ...
Oct 12, 2018
At the end of the day, your products are only as good as their in-the-field performance. It doesn'€™t matter how well they performed in a controlled environment....
chalk talks
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"