Semiconductor
Subscribe to EE Journal Daily Newsletter

Audio is the New UI

In the world of cutting-edge consumer electronics, audio user interfaces reign supreme. In this week’s episode of Fish Fry, we welcome Yipeng Liu from Cadence Design Systems. Yipeng and I discuss how the complexity of mobile codex sample rates is changing the consumer electronic design landscape, why automotive designs present a unique set of audio design challenges, and what lies ahead for the future of audio user interfaces. … Read More → "Audio is the New UI"

The Engineering Long Game

In this week’s episode of Fish Fry, we investigate the role of continuing education in our fast-paced electronic engineering ecosystem. Mike Gianfangna (eSilicon) joins us to discuss how both mentorship and formal education can help address the biggest challenges of chip design and why Mike feels that we should treat electronic design startups like wineries.

Read More → "The Engineering Long Game"

The Next Frontier of Functional Verification

This week’s episode of Fish Fry runs the gamut of electronic design. First, check out how an Italian engineering student built a 3D printer for only twelve dollars! (Spoiler alert: He used recycled parts from three inkjet printers and a flatbed scanner). Next, Breker CEO Adnan Hamid joins us to discuss the controversy around portable stimulus representation models, the future of portable stimulus, and why … Read More → "The Next Frontier of Functional Verification"

Clocks, Xs, and Resets

Does it ever feel to you like, no matter how many new tools features appear, it’s never quite enough? In some cases, you solve one problem – but it doesn’t stay solved. Complexity, scaling, performance and power requirements – they may all catch up to the solution, necessitating further tool refinement. In other cases, new problems arise that were never dealt with before.

< … Read More → "Clocks, Xs, and Resets"

Why Are Design Tools So Bad?

As much as the EDA industry would like us to believe otherwise, it’s almost impossible to find an engineering team who is satisfied with their design tools. More often than not, when chatting with designers about their tools, we get sentiments ranging from “survivable” to “horrible.” The “survivable” end of the spectrum usually amounts to something on the order of, “We managed to get the … Read More → "Why Are Design Tools So Bad?"

September 19, 2017
September 18, 2017
September 15, 2017
September 14, 2017
September 13, 2017
September 12, 2017
September 11, 2017
September 8, 2017
September 7, 2017
September 6, 2017
September 5, 2017
featured blogs
Sep 18, 2017
A friend of mine was saying the other day, “I want to be able to go to my car, type something like New York City , take a nap, and have the car wake me when I get there.” My friend lives in California; barring supersonic auto 2 [*] transportation, it would be a long...
Sep 15, 2017
Glass Weave Skew. For most people it probably sounds like a progressive rock band. But we’re talking about Glass Weave Skew and differential signals. Brandon Gore, Senior Staff Signal Integrity Engineer, and the Manager of Samtec’s Signal Integrity Group, R&D...
Sep 01, 2017
Achronix was delighted to attend the Hot Chips event in Cupertino once again this August. This year saw a bumper turnout, with some very fascinating speakers providing some great insights into the industry. The Achronix team had a chance to meet with many talented people in t...
chalk talks
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"
Pegasus Verification System: Let Your DRC Fly!Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christian Decoin from Cadence Design Systems about the Pegasus Verification System which will let your … Read More → "Pegasus Verification System: Let Your DRC Fly!"
JasperGold RTL Designer Signoff with Superlint and CDCRTL signoff is becoming the preferred design methodology for many teams today. But, verifying that your RTL will give you back the chip you want – the first time – is a challenging task. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence Design Systems about JasperGold, a comprehensive solution … Read More → "JasperGold RTL Designer Signoff with Superlint and CDC"
Insatiable Bandwidth: Why HBM is Right For YouNothing can jam your system up like a lack of memory bandwidth. For many applications, DDR4 isn’t enough to meet  our performance needs. In this episode of Chalk Talk, Amelia Dalton chats with Darren Zacher about using High-Bandwidth Memory (HBM) which brings incredible memory bandwidth to demanding applications. Click here for more information about comprehensive memory … Read More → "Insatiable Bandwidth: Why HBM is Right For You"
Industrial IoT – Smart FactoryIndustrial Internet of Things (IIoT) has a set of challenging requirements for designers. In this episode of Chalk Talk, Amelia Dalton chats with Dan Isaacs of Xilinx about meeting the security, performance, and flexibility demands of IIoT. Click here for more information about Industrial IoT Solutions powered by Xilinx.
Fixed Point, Floating Point – What Are the Needs of DSP Applications?When implementing DSP algorithms, the tradeoff between fixed- and floating-point math can have huge implications on performance and precision. In this episode of Chalk Talk, Amelia Dalton chats with Pushkar Patwardhan of Cadence Design Systems about making the critical decisions on floating-point versus fixed-point. Click here for more information about Tensilica Customizable Processor and DSP IP.