Semiconductor
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Go Configure and Multiply

Where else can you go for not one but two electronic engineering interviews with two of the coolest executives in the biz? Yep, right here. First up, Robert Blake (Achronix – CEO) and I discuss the details of their Speedcore custom blocks, the issues surrounding the efficiency of computation in SoC design, and the benefits of FPGA acceleration core integration. Also this week, Mike Wishart (efabless – CEO) … Read More → "Go Configure and Multiply"

The Biggest SoC/FPGAs

In the decades-long battle between Altera (now part of Intel) and Xilinx, no title has been more hotly contested than “Ours is Biggest.” Way back in the days when real LUTs had 4 inputs, FPGA companies resorted to measuring their density with “system gates” in order to obscure the pathetically small (at the time) amount of logic that could actually be implemented in the programmable … Read More → "The Biggest SoC/FPGAs"

GlobalFoundries Puts Their Cards on the Table

Just over a month ago, GlobalFoundries (GF among friends) had their technology conference, and it would appear that they stored up all kinds of news to release at the same time. Some announcements were more significant than others; we’ll review what’s new here, with a focus on the bigger issues and a passing nod to the others.

I Could Use … Read More → "GlobalFoundries Puts Their Cards on the Table"

Nightmare at Seven Nanometers

The wild wind whistles strange
through the bright gloom of eternal daylight
in the tightly-sealed semiconductor fab.
In the power-assured place where progress never pauses,
where cryptically-coded wafers plod persistently
through mysterious machines in the acrid vacuum
of the multi-billion-dollar bay-and-chase clean room.
Where white-suited phantoms pass silicon slices
through evil rays and deadly potions and spinning saws.
Something is … Read More → "Nightmare at Seven Nanometers"

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featured blogs
Nov 21, 2017
When plotting waveforms in Virtuoso Visualization and Analysis across sweeps you might want to group plots with the same values together, or display each corner in the same color etc. Of course, you can right-click on the plot and select Copy to or Move to and move the plots ...
Nov 20, 2017
When faced with the need for more of something, one possible solution is expansion. This could take many forms but one simple way is extending it to be greater in size, such as adding the dining room table leaves to fit more people around the Thanksgiving table. Samtec’s...
Nov 16, 2017
“Mommy, Daddy … Why is the sky blue?” As you scramble for an answer that lies somewhere between a discussion of refraction in gasses and “Oh, look—a doggie!” you already know the response to whatever you say will be a horrifyingly sincere “B...
Nov 07, 2017
Given that the industry is beginning to reach the limits of what can physically and economically be achieved through further shrinkage of process geometries, reducing feature size and increasing transistor counts is no longer achieving the same result it once did. Instead the...
chalk talks
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"
Pegasus Verification System: Let Your DRC Fly!Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin from Cadence Design Systems about the Pegasus Verification System which will let your … Read More → "Pegasus Verification System: Let Your DRC Fly!"
JasperGold RTL Designer Signoff with Superlint and CDCRTL signoff is becoming the preferred design methodology for many teams today. But, verifying that your RTL will give you back the chip you want – the first time – is a challenging task. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence Design Systems about JasperGold, a comprehensive solution … Read More → "JasperGold RTL Designer Signoff with Superlint and CDC"
Insatiable Bandwidth: Why HBM is Right For YouNothing can jam your system up like a lack of memory bandwidth. For many applications, DDR4 isn’t enough to meet  our performance needs. In this episode of Chalk Talk, Amelia Dalton chats with Darren Zacher about using High-Bandwidth Memory (HBM) which brings incredible memory bandwidth to demanding applications. Click here for more information about comprehensive memory … Read More → "Insatiable Bandwidth: Why HBM is Right For You"
Industrial IoT – Smart FactoryIndustrial Internet of Things (IIoT) has a set of challenging requirements for designers. In this episode of Chalk Talk, Amelia Dalton chats with Dan Isaacs of Xilinx about meeting the security, performance, and flexibility demands of IIoT. Click here for more information about Industrial IoT Solutions powered by Xilinx.
Fixed Point, Floating Point – What Are the Needs of DSP Applications?When implementing DSP algorithms, the tradeoff between fixed- and floating-point math can have huge implications on performance and precision. In this episode of Chalk Talk, Amelia Dalton chats with Pushkar Patwardhan of Cadence Design Systems about making the critical decisions on floating-point versus fixed-point. Click here for more information about Tensilica Customizable Processor and DSP IP.