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Broadcom, Qualcomm, and Call of (Fiduciary) Duty

We’re all in something like our fourth month of sitting and watching the slow motion drama of Broadcom’s attempted acquisition of Qualcomm. It seems everyone has an opinion on whether the merger would be a good thing or bad thing, and debate rages on as the fluid situation repeatedly escalates and then cools. At this point, it’s anybody’s guess whether … Read More → "Broadcom, Qualcomm, and Call of (Fiduciary) Duty"

DVCon and the Big Data Problem

Design and verification technologies are front and center in this week’s episode of Fish Fry. DVCon General Chair Dennis Brophy joins us with a special sneak peak of the 2018 Design and Verification Conference. Dennis and I chat about how the biggest trends are reflected at DVCON, including machine learning, automotive technologies, and big data analysis. We also discuss the addition of shorter format workshops to … Read More → "DVCon and the Big Data Problem"

The Cat-and-Mouse World of Logic Camouflage

We all know that security (or at least talking about it) is all the rage, although most of that attention relates to software. But hardware too? Yes, hardware too. However, today, we’re not going to talk about hardware that’s providing security to something else; we want to talk about protecting the hardware itself as intellectual property (IP).

Reverse engineering by companies like Read More → "The Cat-and-Mouse World of Logic Camouflage"

Wide Bandgap Wakes Up

For the five decades of Moore’s Law, the main thrust of semiconductor technology advancement has been about shrinking geometries, lowering voltages, and lowering power consumption. Silicon CMOS has dominated that domain, of course, and most of the world’s semiconductor production is now CMOS for digital circuits.

Quietly, however, significant progress has been made on … Read More → "Wide Bandgap Wakes Up"

eFPGAs Go Mainstream

For decades, the idea of embedded FPGA fabric has been hanging around the industry like a comic sidekick – providing entertaining conversation, but never really taking part in the plot. The concept seemed solid enough on paper. Put some LUT fabric on your ASIC along with the other stuff and you get additional flexibility, maybe avoiding the almost-inevitable need to park an expensive FPGA right next to your ASIC when … Read More → "eFPGAs Go Mainstream"

Spectre and Meltdown Continuing Coverage

Spectre and Meltdown are possibly the most important (and interesting) security vulnerabilities discovered in the past two decades. Because they capitalize on weaknesses in commonly-used architectural features in many processors, they span numerous vendors, processors, and just about every type of computing device. Billions of processors deployed over the past two decades could be vulnerable.

The EE Journal editorial team is working to bring you the “engineer’ … Read More → "Spectre and Meltdown Continuing Coverage"

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featured blogs
Feb 23, 2018
The IEEE-SA has a policy of keeping standards active by making sure they get a cycle of updates every 10 years. Including Verilog, SystemVerilog has been going on a cycle of updates every 5±1 years since 1995. I wrote here about the updates to 1800-2009 and 1800-2012, and no...
Feb 23, 2018
What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers are currently in transit around the world? It turns out that no one kn...
Feb 22, 2018
We’ve spent a good chunk of the last year building a new on-site search experience for Samtec.com. This update continues that trend with our newly released competitor cross reference search addition. Using this feature, you can access competitor cross reference data for...
Jan 19, 2018
Artificial intelligence (AI) is reshaping the way the world works, opening up countless opportunities in commercial and industrial systems. Applications span diverse markets such as autonomous driving, medical diagnostics, home appliances, industrial automation, adaptive webs...
chalk talks
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"
Pegasus Verification System: Let Your DRC Fly!Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin from Cadence Design Systems about the Pegasus Verification System which will let your … Read More → "Pegasus Verification System: Let Your DRC Fly!"
JasperGold RTL Designer Signoff with Superlint and CDCRTL signoff is becoming the preferred design methodology for many teams today. But, verifying that your RTL will give you back the chip you want – the first time – is a challenging task. In this episode of Chalk Talk, Amelia Dalton chats with Pete Hardee of Cadence Design Systems about JasperGold, a comprehensive solution … Read More → "JasperGold RTL Designer Signoff with Superlint and CDC"
Insatiable Bandwidth: Why HBM is Right For YouNothing can jam your system up like a lack of memory bandwidth. For many applications, DDR4 isn’t enough to meet  our performance needs. In this episode of Chalk Talk, Amelia Dalton chats with Darren Zacher about using High-Bandwidth Memory (HBM) which brings incredible memory bandwidth to demanding applications. Click here for more information about comprehensive memory … Read More → "Insatiable Bandwidth: Why HBM is Right For You"