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Programmable Pile of Parts

FPGAs were conceived as “do anything” chips – Jacks of all Trades. Sure, they were crazy expensive for the number of effective gates they offered, they were a lot slower than custom logic doing the same task, and they drank copious quantities of coulombs getting the job done, but they could be programmed to do exactly your bidding. In a lot of designs, that made the FPGA the no-longer-missing link – … Read More → "Programmable Pile of Parts"

Zap! Zap! Zap! GlobalFoundries’ UHV 180nm Process Hits 700V

Thunder is good, thunder is impressive; but it is lightning that does the work. – Mark Twain

With all the media hype and heavy emphasis on the leading-edge semiconductor process technologies that will soon reach single-digit nanometer numbers, working-class process technologies often get no respect. That’s why I was so pleased to learn that GlobalFoundries Read More → "Zap! Zap! Zap! GlobalFoundries’ UHV 180nm Process Hits 700V"

An MRAM Cell that Competes with SRAM?

Anything you do can be done efficiently or not. Whether it’s driving (mpg?), playing sportsball (results/energy spent?), or walking the dog (who pulls whom?), you can be efficient or not. Obviously, higher efficiency is better – assuming you care (sometimes spending energy worrying about efficiency can be inefficient). So… what if you could identify an improvement for an activity you care about that, by itself, … Read More → "An MRAM Cell that Competes with SRAM?"

PowerVR AX2185 Accelerates Neural Nets

“The greatest danger of AI is that people conclude too early that they understand it.” — Eliezer Yudkowsky

Sometimes accidental discoveries are the best ones. Teflon was supposed to be a refrigerant. The first heart pacemaker was designed as a measuring device, but inventor Wilson Greatbatch put in the wrong resistor value. And Play-Doh was created to clean wallpaper.

Read More → "PowerVR AX2185 Accelerates Neural Nets"

Computing at a Crossroads

Computing is at a crossroads. For decades, we have surfed the exponential wave of Moore’s Law, tuning and tweaking the various von Neumann architectures, resizing caches, redefining pipelines, debating RISC vs CISC, messing with memory structures, widening words, predicting branches, and generally futzing around until we reached a point where we could claim victory for another node. We have built various schemes for … Read More → "Computing at a Crossroads"

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featured blogs
Jun 22, 2018
A myriad of mechanical and electrical specifications must be considered when selecting the best connector system for your design. An incomplete, first-pass list of considerations include the type of termination, available footprint space, processing and operating temperature...
Jun 22, 2018
You can't finish the board before the schematic, but you want it done pretty much right away, before marketing changes their minds again!...
Jun 22, 2018
Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology services and, in particular, something we called Virtual CAD. The idea of Virtual CAD was to allow companies to outsource their CAD group to Cadence. In effect, we would be the CAD group for...
Jun 7, 2018
If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn'€™t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors '€” then progressing to gates, ALUs...
May 24, 2018
Amazon has apparently had an Echo hiccup of the sort that would give customers bad dreams. It sent a random conversation to a random contact. A couple had installed numerous Alexa-enabled devices in the home. At some point, they had a conversation '€“ as couples are wont to...
chalk talks
Debug and Verify FPGA Algorithms with MATLAB and Simulink   Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design. Click here for more information about how to verify VHDL and … Read More → "Debug and Verify FPGA Algorithms with MATLAB and Simulink"
Mixed-Signal Digital Complexity Explosion   Mixed-signal design is becoming increasingly complex, and our old tools and methods just won’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe of Cadence Design Systems about the changing mixed-signal landscape and how Cadence’s robust suite of mixed-signal design solutions can solve your toughest problems. Click here … Read More → "Mixed-Signal Digital Complexity Explosion"
Moving Between FPGA and ASIC with High-Level Synthesis Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible. But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow. Click here for more … Read More → "Moving Between FPGA and ASIC with High-Level Synthesis"
Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP   Neural networks are taking over a broad range of exciting applications these days. But, the amount of computation required for neural network inferencing can be daunting. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai of Cadence Design Systems about some new processor IP designed specifically for neural network inferencing. … Read More → "Scaling Embedded Deep Learning Inference Performance with Dedicated Neural Network DSP"
Cadence Xcelium Parallel Simulator: Third Generation Parallel VerificationGetting the best RTL simulation performance is a combination of improving single-core speed and cleverly partitioning the task so that parallel machines can give you the kind of performance boost you’d expect. In this episode of Chalk Talk, Amelia Dalton chats with Dave Lidrbauch from Cadence Design Systems about Xcelium – Cadence’s third-generation parallel RTL simulation … Read More → "Cadence Xcelium Parallel Simulator: Third Generation Parallel Verification"
Pegasus Verification System: Let Your DRC Fly!Design rule checking (DRC) can be the one of the biggest bottlenecks in getting a chip out the door. The computation power required for a large DRC run can be staggering. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin from Cadence Design Systems about the Pegasus Verification System which will let your … Read More → "Pegasus Verification System: Let Your DRC Fly!"