I once commented to a colleague that every EDA presentation ever given follows a basic script: Presenter: Moore’s Law!Audience: Oh no! What shall we do?Presenter: Don’t worry. We have a new EDA tool that’ll save you.Audience: What a relief. If that is true, then every semiconductor presentation might have an analogous script: Presenter: Moore’s Law!Audience: … Read More → "Cheap Gate Update"

It never makes the marketing materials. You don’t see an ad saying “New Super RISC Core is Stickier than Ever!” There is generally no mention of the word “sticky” in datasheets, white papers, or application notes. Suppliers of Intellectual Property (IP) cores (the overly-broad label that’s commonly applied to pre-engineered components that you can drop … Read More → "Sticky Business"

The news has been slowly leaked like the plot to an upcoming summer blockbuster movie. First, there is “the teaser.” In movies, this is a 30 second preview that gives only the most basic hint of the film. In our case, this was Xilinx’s ASMBL architecture announcement that came out in December 2003. Xilinx outlined … Read More → "Virtex 4 Gets Real"

Unbelievable! FPGA Journal is running a feature article on a Xilinx organization change? What’s next, an exposé on Altera’s new carpets at corporate headquarters? Maybe an in-depth analysis of Lattice’s motivation for switching from Seattle’s Best to Stumptown coffee in their cafeteria? What happened to the concept of discriminating technical journalism? While org-chart changes are … Read More → "What’s Your Persona?"

Professor Jason Cong’s office on the campus of UCLA is full, but not cluttered; important, but not pretentious; functional, but not over-designed. A wall of bookshelves that overlooks the desk and conference table is filled with proceedings from probably every technical conference ever to approach the subject of programmable logic design. One gets the impression … Read More → "Jason Cong"

The first explorers came with Karnaugh maps and truth tables. Complex combinational functions could be concentrated in programmable logic devices more efficiently than with random logic parts or large, sparse ROMs. As these early PAL pioneers blazed trails into a new frontier of logic design, a culture of design methodology grew around them, and the … Read More → "Methodology Melting Pot"

His eyes meet the goalie’s steely gaze. He refuses to be stared down. In his mind, he calmly visualizes the moves to come, picturing success at each step. He will take three measured strides before his right foot strikes the ball slightly below center. He will follow through with his leg and keep his eyes … Read More → "Digital Do-Overs"

Why do we choose FPGAs? Usually because we want to get our design to market faster, cut our design cost and risk, and have more flexible, versatile products at the end. Because the process of customizing the FPGA is getting increasingly efficient, the development of a working board is rapidly becoming the long pole in … Read More → "Mod Modules"

The contest begins. On the left side of the hall (the “blue” corner), the FPGA design team iterates through the design loop with their high-performance design tools, looking for the optimal placement to reach timing closure. As paths are probed and placements are optimized, it becomes apparent that the problem is the pin assignment. After … Read More → "Board Room"

Cyrus Tsui doesn’t believe in the “Flanking Attack.” He likes the head-on confrontation, even with an entrenched opponent. He’s not intimidated by numbers or humbled by setbacks. He is a true competitor, and has been in the industry long enough to know that the rules of the game change regularly. This month, Lattice Semiconductor, where … Read More → "Cyrus Tsui"