It never makes the marketing materials. You don’t see an ad saying “New Super RISC Core is Stickier than Ever!” There is generally no mention of the word “sticky” in datasheets, white papers, or application notes. Suppliers of Intellectual Property (IP) cores (the overly-broad label that’s commonly applied to pre-engineered components that you can drop into your design, saving time, errors, and design effort) tout the speed, configurability, reliability, density, and power efficiency of their offerings, but never the “stickiness.” Unless you listen carefully to conversations in hallways, meeting rooms, and strategy planning sessions at EDA, FPGA, and even IP vendors, you might never become acquainted with the concept of “stickiness” at all.
What, then, is “sticky IP”? Simply put, “sticky IP” refers to the type of IP cores that, when designed into your circuit, make it difficult for you to transition to a different silicon, software, or IP vendor. This marketing strategy is not new. It is at least as old as the concept of selling razors at a loss so people will be locked into buying your blades instead of your competitor’s, or almost giving away the camera so people will have to buy your film. In many circumstances, the consumer benefits along with the supplier. In the case of IP, the cost of development is relatively high, and the audience is small. Amortizing those development costs over such a small audience can be a significant challenge for suppliers trying to make a business just from the IP itself. Consolidating the sales and distribution of IP with other mandatory components (silicon, software tools, etc) reduces the sales, marketing, and operations overhead in the process and generally gives a higher value to the consumer.
IP is made sticky either by technical means (moving your design with the IP block included to another technology or tool just won’t work without significant engineering effort) or by contractual means (the license agreement restricts use of the IP to a particular platform). Stickiness can also be either intentional or accidental on the part of the supplier. In most cases, stickiness is a simple business decision involving protecting a significant investment in the development of high-performance IP cores to leverage the sale of silicon, or to differentiate silicon or tool offerings from those of a competitor. If a vendor invests in IP to boost their main business, the last thing they want to see is their IP being used to the advantage of a competitor.
As we all know, engineering is an art form based on balancing compromise. Engineers are trained to weigh the merits of opposing requirements and come to a solution that has an acceptable mix of performance, safety, and cost (along with a host of less-tangible factors.). When it comes to including IP in a digital system design, it is important for engineering teams to understand the relative stickiness of the IP they’re using, and to make a responsible judgment in how that stickiness impacts their overall design goals. If, for example, a design is targeted to a single FPGA family, is not slated for future migration to a lower-cost ASIC technology, and will not be re-used in the future as part of another project, stickiness of IP is of no concern whatsoever.
If, on the other hand, your design is really targeted at an ASIC, but you’re using FPGAs to prototype it, you should consider carefully before using any vendor-supplied IP as a shortcut. The core that saves you time and effort today in your prototyping might be your worst design nightmare when you get ready to move to the final ASIC version. If you get to the final stage of your design only to find out that you can’t meet timing with that PCI core, or that the DSP block you used is licensed only for the FPGA you’re using, you’re faced with a tricky last-minute design problem, and a prototype that doesn’t necessarily work the same way that the production version will. “It’s important to realize that most ASIC designs go through some kind of FPGA prototyping phase, so IP supporting this development needs to be able to function in both environments,” says Phil Dworsky, Director of Marketing, DesignWare IP, Synopsys. “This means that the designer absolutely cannot tolerate ‘sticky IP.’”
Some IP is just sticky by nature. In order to meet timing on some performance-critical modules, FPGA vendors must carefully craft the IP block to use custom-designed hard modules that only appear only on their proprietary devices. “As we do the IP design,” says Gordon Hands, Strategic Marketing Manager at Lattice Semiconductor, “we’re trying to best tailor the IP to take advantage of what we put into the device architecture. The IP cores that seem to be most popular right now are high performance I/O standards such as PCI and double data rate memory. In these cases, IP development is tightly coupled to silicon architecture for performance reasons.”
Often, FPGA vendors understand that designs will need to migrate beyond their offerings, and they make allowances to facilitate the transition.
“There are definitely times when a company sees significant enough differentiation in the IP offered by a particular FPGA or ASIC vendor to accept the ’lock-in‘ that comes with the IP,” continues Synopsys’s Dworsky, “Increasingly, however, there are cases where these vendors are willing to license the IP for use on other process technologies.” Altera, for example, offers its IP (including its popular Nios RISC cores) for ASIC migration use for an additional fee. This is particularly important in the case of soft-core processors, which have been labeled the “stickiest IP of all.” The re-design effort involved in re-coding embedded software (particularly if written in assembly for maximum performance on a specific processor) can dwarf almost any other IP migration task in terms of development and debugging time and cost.
“IP developments such as Nios do indeed require large development teams, and a focus and long term commitment by management to be in the business,” says Justin Cowling, director of marketing for Altera’s IP business unit. “Embedded microprocessors (such as Nios II) historically have been the most sticky pieces of IP, especially for customers who program in assembly, anxious to extract the last ounce of performance from their core.”
Even the processor situation is improving, however, as embedded development teams move more toward high-level languages and standardized RTOS environments. “Over the last couple of years,” continues Cowling, “there has been a migration by the software community to C-language entry, and that has dramatically reduced the stickiness of microprocessor IP.”
As much as stickiness of IP can help boost the business of a silicon or tool offering, a similar advantage can be gained by breaking the lock of sticky IP. “As an EDA provider, we also have noticed silicon vendors creating and promoting IP that is tied to their silicon and is hard to change once designed in,” says Synplicity’s Jeff Garrison, Director of
Marketing for FPGA Tools. “A big part of the value of using a vendor-independent tool like Synplify is that IP such as RAM and DSP blocks can be inferred from the HDL source and then optimized for the specific FPGA from the same environment. This makes it much easier to port a design to several different FPGAs.”
Bruce Edwards, Executive Director, Altium Limited, sees the same opportunity. “Altium has been engaged in some serious pioneering work with the potential to create a de-facto standard for ‘non-stick’ IP. During the development of our Nexar product, which provides an HDL-free systems-level design environment, we sourced our own IP cores for some popular 8-bit controller/processors (8051, PIC, Z80) and peripherals. These are supplied to Nexar users as component models that can be wired together in a schematic editor to create a complete system. The trick is that our IP-based component models are linked to pre-synthesized / pre-verified entities that are fully optimized for each specific FPGA architecture. This linking is all done in the background without any user interaction and can be re-targeted for a different FPGA, on the fly. That’s about as ‘un-sticky’ as you can get.”
Even within your design methodology, there are steps you can take to protect yourself from excessive stickiness, and make your design more portable and re-usable. Synplicity’s Garrison continues; “Depending upon how the HDL code was written, there could be a large difference in portability. For example, if the HDL code had direct instantiations of a particular FPGA vendor’s RAM blocks, the designer would have to go back in the HDL source and modify the code to target a different vendor. This is time- consuming and error-prone. If, on the other hand, they had written the HDL in a vendor-independent way so that the RAM can be inferred, Synplicity’s Synplify tool can implement the design optimized for any vendor from the same RTL source, making the migration easier and faster.”
The commercial IP industry is relatively new, and it has struggled from the beginning to find a sustainable, workable business model. As the target customer has morphed from well-funded long-term ASIC development teams to more nimble, efficient FPGA teams, that business model has been held to the fire and continues to adapt. “ Before Altera entered the IP industry,” says Altera’s Cowling,” “this natural “stickiness” was extremely costly to the customer. The IP vendor would almost always license their IP “by project”. The impact was that when the customer wanted to use that block again for a follow- on project, they would have to pay again (and again, and again, and again…). ASIC low volume, sticky IP with a high repeat licensing rate was the norm and how the IP industry made money.”
“When Altera entered the IP industry,” Cowling continues, “the dynamics completely (and permanently) changed. IP for FPGAs represent a high-volume IP business that was lacking before. The high volume rate was the first enabler for the IP vendors to lower their prices. Following that, Altera innovated with the IP model and was the first vendor ever to provide free IP evaluation, through OpenCore.”
Actel has a similar “try before you buy” approach to IP distribution. “Actel delivers IP in 3 forms: evaluation, netlist, and RTL source,” says Ian Land, senior manager, IP marketing. “Evaluation versions are not for production, and are limited to demonstrating the capabilities of the IP to the user within Actel’s tools. Evaluation versions of Actel’s IP cores are distributed without charge and are not portable to competitive tools or devices. Netlist versions of Actel’s IP cores are Actel-specific (due to the nature of a netlist) and therefore, are difficult to port to other technologies. All of Actel’s IP cores are also available as RTL source that can be ported to other technologies (even competitors’), with varying levels of difficulty, depending on the complexity of the core and the unique features that exist due to optimization for Actel FPGA architectures. Actel has customers who opt for RTL source so they can have the option (contractually granted) to take their design to competitive silicon devices, (most often ASICs,) at a later date.”
IP is certainly a high-value offering, and there is plenty of room in the market for both Teflon-coated and Super-sticky versions. For IP to be completely neutral, design teams must be willing to pay a substantial price for their share of the development of highly reliable, reasonably re-targetable, passably performing cores. There will always be opportunity for FPGA and EDA vendors to subsidize the development of even higher-performance modules to differentiate their offerings and lock customers into their technology or methodology. If you’re waiting for some fantasy-driven future where highly portable, sophisticated IP is available license-free for download from a variety of sources, you’ll probably be disappointed. If, on the other hand, you make a reasonable engineering effort to understand the trade-offs you make when incorporating any piece of IP into your design, you should experience a gradual increase in productivity and design quality as you take advantage of the fruits of the IP industry’s labor.