feature article
Subscribe Now

Cheap Gate Update

News from the Low-Cost Frontline

I once commented to a colleague that every EDA presentation ever given follows a basic script:

Presenter: Moore’s Law!
Audience: Oh no! What shall we do?
Presenter: Don’t worry. We have a new EDA tool that’ll save you.
Audience: What a relief.

If that is true, then every semiconductor presentation might have an analogous script:

Presenter: Moore’s Law!
Audience: Oh boy! What do we get?
Presenter: Bigger, faster, cheaper.
Audience: Yaaay!

This week, we’re celebrating the “cheaper” part of that script, applied to programmable logic. We’ve covered several announcements over the past year that, taken together, have significantly changed the programmable logicscape. Beginning with Altera hitting the $12 USD for 1 million gates watermark with their original Cyclone series, the capability and diversity of low-cost FPGA lines have headed steadily up and to the right.

While the “to the right” part of that graph isn’t particularly interesting (hey, time marches on…) the “up” part has some exciting news for patrons of programmables in the high-volume, low-cost arena. Contending for your monetary mindshare are three FPGA families and, um, another FPGA family pretending to be a CPLD.

Leading our list is the first-to-market 90nm low-cost FPGA family from Xilinx, Spartan 3. Lest we be confused, Spartan 3 is the aptly named Xilinx family that followed Spartan and Spartan 2. Since we’ve received over 50 reader e-mails on this question, maybe we should re-clarify the Xilinx lines. The latest two Xilinx families, both based on 90nm design rules, are Spartan 3 (low cost) and Virtex 4 (high performance/density). The previous generation (130nm design rules) included Spartan 2 and Virtex II (and Virtex II-Pro). Virtex 3 does not exist. It apparently fell into a Virtex vortex and those who have gone in search of it have never returned. Xilinx claims that Virtex II Pro is actually the missing Virtex 3, but DNA tests have yet to be performed.

Now back to our “low-cost” discussion. Spartan 3, which Xilinx recently announced has passed the “one million units shipped” milestone, is available in densities ranging from 50,000 to 5 million system gates. In more understandable terms, the family ranges from 1,728 to 74,880 logic cells, with proportional servings of other nice features such as block RAM (72K-1872K bits), I/O (124-784 single-ended), and 18X18 multiplier blocks for DSP use (4-104). Xilinx claims a 326MHz system clock rate for the family.

Xilinx says the Spartan 3 devices in quantities of 250K at the end of 2004 are less than $6.50 USD for the XC3S50, XC3S200, and XC3S400 Spartan 3 devices, with 50,000, 200,000, and 400,000 system gates, respectively, and under $12.00 USD for the XC3S1000 device with one million system gates. Pricing depends on many factors, such as volume and delivery date, so you’ll need to check with your distributor for details.

Altera, who threw down the gauntlet in the low-cost wars with their $12.00 USD, million-gate Cyclone device, has raised the ante with their Cyclone II family. Cyclone II is a 90nm update of the Cyclone series, available in densities ranging from 4,608 Logic Elements (LEs) to 68,416 LEs. Do you remember your conversion from Altera LEs to Xilinx LCs? No? Well, shame on you. Go back and re-read our “Terminology Tango 101” article. It won’t make things all that much clearer, but you’ll have fun doing the research. By our math, however, the Xilinx family starts a little smaller than the Altera offering and goes a little larger in terms of equivalent 4-input look up tables (LUTs).

Nobody eats just vanilla ice cream anymore, though, do they? Plain old LUTs are not the only thing to measure these days. There are also the “sprinkles,” extra features like multipliers, RAM and I/O. Cyclone II ranges from 104K bits of block RAM to about 1MB on the high end. For getting data on and off the chip, Cyclone II offers 142-622 I/O pins, and on the 18X18 multipliers, Cyclone II ranges from 13 to 150. Comparatively, then, Altera is offering a slightly narrower range on all the “sprinkles” except for multipliers, where they’ve piled on a whole extra handful.

On availability, Altera’s 90nm Cyclone II family is lagging Xilinx’s Spartan 3 offering, with the family members scheduled to ship at various times between Q1 and Q3, 2005. What we really have, however, is a competitive cycle between the two companies that’s about six months out of phase (with a one year period) where each company can claim an advantage at almost any time based on: the previous family shipping in volume (Altera’s Cyclone at this point), the current family ramping up to volume (Xilinx’s Spartan 3), and the next family making its run to production (Altera’s Cyclone II).

Altera lists pricing for Cyclone II based on $22 USD for an EP2C35 device at quantity 250,000 in February 2005. That’s 33K LUT-like cells for $22 compared with Xilinx’s 17,280 cells for $12.00 or 29,952 for “less than $20”. If we do the math, that comes out as 66 cents per 1000 LUTs for Altera, and 69 cents per 1000 LUTs or 67 cents per 1000 LUTs for Xilinx (Altera in February 2005 and Xilinx at “end of 2004”). Confused? Hang on; we’ll make it even more complicated.

In sailboat racing, a special set of tactics is used when “match racing,” because there is only one other competitor. Normally, Xilinx and Altera are engaged in a match race, and they each typically employ strategies that leverage the existence of a single opponent. Lattice Semiconductor is now assuming the role of spoiler by introducing a third competitor into the mix, and the match racing tactics will have to go out the window.

This summer, Lattice introduced their “EC” families (internally known as “El-Cheapo,” in case there was any doubt about their competitive intentions). Lattice’s new families (one with DSP features and one without) range from 1.5K to 41K LUTs (approximately equal to Altera LEs and Xilinx LCs). This means, in terms of logic fabric, that they start a little smaller than the Xilinx Spartan 3 family, but don’t extend as far as either competitor’s families on the large end. Looking at the “sprinkles” specifications, Lattice’s EC and ECP families range from 18K to 645K bits of block RAM and 112-576 I/Os.

Lattice has done a clever partitioning of the family into DSP and non-DSP versions, however, so you may be able to buy a device that offers just what you need and nothing more (if, for example, you don’t want to pay for a bunch of multipliers you’re not planning to use). If you do want DSP, Lattice has gone a step farther than their competitors with their “sysDSP” digital signal processing blocks. Lattice’s DSP blocks offer features comparable to other vendors’ high-end FPGAs, including the ability to do Multiply-accumulate (MAC) functions within the block and the ability to configure multipliers to be x9, x18, and x36. This extra capability may be valuable to designers targeting high-performance DSP algorithms to low-cost FPGAs. The non-DSP (EC) family also gains advantage of smaller die size by omitting the multipliers.

Lattice’s announced pricing is quoted on volumes more often encountered by FPGA design teams. Whereas Xilinx and Altera are both quoting at 250K price points, Lattice quotes are in volumes of 1K. Lattice says an ECP20 sells for $59 and an EC20 sells for $49 at that volume. Their prices work out to between $2 and $3 per 1000 LUTs right now. Can you compare these Lattice apples with Xilinx and Altera’s oranges? No. Once again, you’ll need to call your favorite distributor and compare prices in the actual volumes you need, for the actual devices you need, at the actual time you need them. Any other price comparison is basically useless. Also, take into account the total system cost for the FPGA portion of your design, as you may find differences in things like power supply and configuration circuitry cost. Lattice, for example, has designed the EC/ECP families to be configured by low-cost SPI serial flash memories.

If you’re looking for smaller devices, like the idea of non-volatility, and don’t mind nodding and winking as you pretend your device is actually a CPLD, Altera’s Max II family also deserves consideration in this group. Max II ranges from 240 to 2,210 logic elements. At $7.00 USD for 2,210 LEs, (quantity 500K) they may be even a bit cheaper per LUT than the low end of Xilinx’s Spartan 3 family. If you just don’t need that many gates, they also give the lowest unit cost of any family in this write-up at $1.50 for 240 LEs. Max II is strictly vanilla, however. Don’t go looking for DSP blocks, multipliers, or other fancy features only found in larger families.

We’ve only scratched the surface here of what these devices can do. Both the Xilinx and Altera families can easily implement their respective vendors’ soft-core 32-bit RISC processors (Xilinx’s MicroBlaze and Altera’s Nios II). When combined with the I/O, memory, and DSP capabilities of these families, they offer a compelling solution for embedded designers wanting to create high-capability systems at the lowest possible cost with maximum flexibility. Already, we’re seeing rapid adoption of these devices in applications where FPGAs have rarely been seen, such as high-volume consumer, automotive, and industrial applications.

Remember to check often for changes, as this is a market that is seldom static. When the vendor or distributor comes to your company and starts his presentation with “Moore’s Law,” be ready with your response… “Wow!”

Leave a Reply

featured blogs
Dec 4, 2023
The OrCAD X and Allegro X 23.1 release comes with a brand-new content delivery application called Cadence Doc Assistant, shortened to Doc Assistant, the next-gen app for content searching, navigation, and presentation. Doc Assistant, with its simplified content classification...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Bluetooth LE Audio
Bluetooth LE Audio is a prominent component in audio innovation today. In this episode of Chalk Talk, Finn Boetius from Nordic Semiconductor and Amelia Dalton discuss the what, where, and how of Bluetooth LE audio. They take a closer look at Bluetooth LE audio profiles, the architecture of Bluetooth LE audio and how you can get started using Bluetooth LE audio in your next design.
Jan 3, 2023