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Digital Do-Overs

Leveraging Reprogrammability

His eyes meet the goalie’s steely gaze. He refuses to be stared down. In his mind, he calmly visualizes the moves to come, picturing success at each step. He will take three measured strides before his right foot strikes the ball slightly below center. He will follow through with his leg and keep his eyes riveted to the goal as the penalty kick tracks an arcing path through the air, catching the upper right corner of the net just out of the goalie’s reach. He exhales and begins the carefully choreographed sequence. As he nears his third step, a flash of light catches his eye. It distracts him for only an instant, but it is enough. The kick goes wide, and the ball bounces off the front of the approaching vehicle.

“Do overs! Do overs! Interference! There was a car!” shouts one of his teammates. The boys gather around, and after a brief negotiation, the goal is adjusted in the street, time is rewound, and the sequence begins again. The mistake is erased. The wrong has been righted, and fairness prevails.

A short distance away, his mother is putting the finishing touches on an archive before sending her team’s ASIC design away for fabrication. She double-checks the list of files to verify that everything will be copied to the CDs. The project is a few weeks behind and pressure is mounting on the team to complete the design so the market window will not be missed. As she moves the final few files into the archive, the phone rings. It distracts her for only an instant, but it is enough. She inadvertently copies an old version of the netlist, one in which a control signal is incorrectly inverted.

Six weeks and a half-million dollars from now her samples will come back bad. It will take her only twenty minutes to find the problem, but it will be too late. There will be no do-overs. In the world of ASIC design, fairness is not part of the equation.

For former ASIC designers, FPGAs have always held a strong attraction due to their forgiving nature. Mistakes, an inevitable consequence of the human condition, can be quickly resolved on the fly. Even after parts are mounted to production boards and streaming off the assembly line, a design error can be corrected without compromising the schedule or incurring major cost penalties.

Reprogrammability is more than just a free ticket for do-overs, however. Increasingly, savvy engineers are finding new and novel uses for FPGAs’ flexible features that the suppliers probably never foresaw. Since it takes just a few milliseconds to reconfigure an SRAM FPGA, there are functional possibilities available that extend far beyond simple error correction.

Many systems companies produce a range of products with varying functionality at differing price points. Often, the cost of manufacturing and inventorying all the variations can have a significant impact on profitability. Suppose the circuit board on all the variants could be identical. Only one part number could be inventoried, and configuration of the FPGA could determine the feature mix at the end of the process. Not every design lends itself to this approach, but for many applications, the potential cost savings throughout the supply chain are substantial.

For some applications, a similar approach can be used to allow customers to purchase product upgrades in the field. If a new configuration of the FPGA can turn on advanced features, margins on upgrades for the supplier can be significant, and the customer is better served by eliminating the obsolete version of the product and allowing a field upgrade rather than replacement.

Reprogrammability can be tapped to get new products to market faster as well. Often, with cutting-edge products, underlying standards are in constant flux during the early market. Suppliers that ship before the standards are locked risk having non-conforming systems in the field and alienating customers by failing to support subsequent standards. If the variable standard can be isolated to a programmable logic component, however, the product can be shipped early, capturing critical market attention, with the confidence that customers can be supported with upgrades as the technology and standards mature.

Suppliers of Windows-based PC hardware have found an established channel for delivering configuration changes to customers. Pinnacle Systems’ new Movie Box Deluxe configures its Altera Cyclone FPGA using a bit stream embedded in the Windows driver files. Since PC users are already accustomed to downloading driver upgrades from the internet, Pinnacle had a ready-made delivery mechanism for FPGA configuration upgrades. This enabled Pinnacle to substantially reduce product risk, support the customer with easy-to-install field upgrades, and avoid the need to develop a custom delivery system for their product upgrades and patches.

Clever designers have also found ways to leverage reprogrammability to increase the effective logic density of their FPGA device, and thus lower product cost. Also in the MovieBox, Pinnacle took advantage of the modal nature of their product and designed the system to reconfigure the FPGA with one of three different configurations depending on the current mode of operation. This made the Cyclone FPGA into effectively three devices in one, and significantly reduced the device density required compared to a statically configured part.

Development teams such as Nallatech of Scotland have also found ways to use reprogrammability to make the FPGA a powerful design tool in developing its own configuration. As we discussed in a previous feature article, Nallatech turned a Xilinx FPGA with a MicroBlaze soft-core processor and embedded debugging and performance monitoring tools into a super-efficient, low-cost hardware/software co-design tool. Nallatech developed their entire FPGA application in C and ran it on the embedded MicroBlaze at reduced speed. Then, using the embedded performance profiling tools, they isolated software routines that created the biggest performance bottlenecks and re-coded them in RTL as hardware blocks. By iteratively reconfiguring the device and converting the most significant bottleneck to hardware at each step, they were able to deterministically optimize the hardware/software partition without the usual guesswork and inaccurate estimates. With the embedded code already running on the actual target hardware, the performance profile was extremely accurate, and converging on an acceptable partition became a relatively straightforward task.

We have often discussed the merits of FPGAs as DSP engines, and reconfigurability plays a big part in this application space as well. Adaptive algorithms that tune constants or even alter the algorithmic flow through the datapath can be accommodated by designing in reconfiguration of the FPGA. While FPGAs are certainly more complex to reconfigure than the typical DSP processor, it is compelling that the significant performance advantages of FPGAs can be realized without giving up the flexibility of programmability.

For the same reasons that FPGAs make excellent DSP platforms, reprogrammable devices can be set up as super-high-performance reconfigurable computing engines. Leveraging algorithm-to-architecture compilers that generate hardware descriptions from code such as C or C++ as well as custom processor generators, FPGA-based compute engines can reach far higher performance levels at a fraction of the cost of traditional processor-based architectures. In addition to hardware acceleration and custom processor design, state-of-the-art embedded soft-core processors such as Altera’s Nios II can be implemented in large numbers on a single FPGA, creating a massively parallel processing environment.

As design teams become more comfortable, familiar, and experienced with the idea of reprogrammable devices, new innovations are sure to emerge. Technology is at its best when it enters applications never envisioned by the original designers. While do-overs are an attractive and compelling benefit for logic designers and street athletes alike, look to the future for programmable logic to make its own new set of rules that far transcend simple correction of the frequent injustices inherent to the digital design process.

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