feature article
Subscribe Now

Board Room

Mentor Tackles FPGA on PCB

The contest begins. On the left side of the hall (the “blue” corner), the FPGA design team iterates through the design loop with their high-performance design tools, looking for the optimal placement to reach timing closure. As paths are probed and placements are optimized, it becomes apparent that the problem is the pin assignment. After swapping a few I/O constraints around and re-running place-and-route, the design clears timing analysis with flying colors. Positive slack for all!

On the right side of the hall (the “red” corner), this is all bad news. The board design team had a pretty solid layout done based on the old pin assignment. When the new constraints fly in the door scrawled on a paper airplane from across the hall, they spend hours re-creating the design only to find out that their carefully matched bus traces are now scattered to the four winds. The board design team tries to retaliate with pin-assignment changes of their own, but the FPGA team has already left for vacation. The red team is left to trombone their way to tuned trace lengths, wasting precious board space and increasing design cost.

As FPGA tools have evolved over the past few years, the basic task of FPGA design has gotten easier. LUT-for-LUT, it is now faster than ever to get a working FPGA design loaded into your device. FPGA synthesis and place-and-route tools have continued to improve in speed, stability, and quality of results. According to FPGA Journal’s 2003 FPGA market study, these “core” steps in the design process new occupy less than 1/3 of the overall FPGA design cycle.

The same trend has not been seen on the board design side, however. The task of getting an FPGA to work on a production board has become ever more difficult. Higher pin counts, higher operating frequencies, and denser packaging technologies have made the board design problem more and more challenging. In addition, the constant flux of pin assignments characteristic of FPGA design requires significantly more board rework than is required when using comparatively more stable standard parts and ASICs.

Mentor Graphics recently announced a new suite of capabilities for their popular board design tools aimed directly at the challenges faced by designers of FPGA-based systems on boards. The new tool, called “I/O Designer,” handles bi-directional mapping of pin assignments between the PCB and FPGA design environments. I/O Designer provides a graphical interface that allows viewing and editing of pin assignments in a package view. The tool then creates I/O constraints for both PCB and FPGA layout, maintaining synchronization between the two domains.

With FPGA pin counts skyrocketing and an increasing number of board designs incorporating multiple FPGAs, manual or spreadsheet-based exchange of pin assignments between FPGA and PCB teams is quickly becoming unwieldy. For a single FPGA of 200 pins or so, the problem is easy to solve with homegrown manual methods, but with designs containing two or three FPGAs with upwards of 1,000 pins each, the complexity of the problem explodes. In addition, the increasing operating frequency and tighter I/O constraints of today’s devices demand careful consideration of the effect of pin assignment on board-routing-related timing performance. When crossing the line from on-chip timing optimization to board timing optimization, pin assignments are often changed many times in order to reach a compromise that will yield satisfactory results on both sides of the I/O pad.

I/O Designer provides a single environment that can be leveraged by both sides of the design team to make and understand I/O assignments while keeping the equation in balance. I/O designer sits between the FPGA design and PCB design flows, exchanging information with both environments. (Fig. 1)

On the FPGA vendor side, Mentor says the new tool supports all Actel, Altera, and Xilinx FPGA families. In addition to symbol and fractured symbol generation (some FPGA designs need to be split into multiple symbols to manage the high pin-count on reasonable sized schematic sheets), the new solution also has an interface that provides graphical drag-and-drop pin assignment and swapping. The tool has the capability to enforce pin swap design rules so that illegal assignments or swaps are not made.

I/O Designer can operate before FPGA synthesis and place-and-route, so board designers can get an early start on the design with assumed pin assignments, and then evolve their design as the FPGA takes shape. Once the design is underway from both teams, pin swaps made in either the FPGA or PCB layout environments are automatically passed through to the other side of the house.

While I/O Designer is not yet a panacea for PCB problems, it is certainly a step in the right direction. FPGA and EDA vendors have made enormous progress developing and integrating high-quality tools for FPGA design, but tool support for the part outside the pins has been much slower in coming. Within the past months, however, a series of EDA-company announcements such as Cadence’s “Design-in kits” and Mentor’s own previous “FPGA BoardLink” indicate that the industry is beginning to understand the need to solve the critical design issues in this area of growing concern.

I/O Designer supports all of Mentor’s board design offerings including Board Station, Expedition, and PADS and connects on the FPGA design side to Mentor’s own FPGA Advantage as well as FPGA vendor-supplied tool suites. Mentor says the tool is available now, priced starting at $10,000 US. While it won’t end the long-standing battle between the blue and red teams of FPGA and PCB design, it at least provides a neutral ground where the compromises can be worked out on a level playing field. It also assures that last minute ECOs don’t blow your design by manual mis-translation of I/O constraints passed between teams.

What should we look for in the future? With the rapid emergence of gigabit serial I/O, robust support for differential signal pairs will become critical. Also look for greater automation of the process beyond the largely manual design flow offered by I/O Designer. Additionally, since most FPGA design work these days involves a development/prototyping board, and these boards often have considerable sophistication in their layout and connection to key peripherals, it would seem that PCB design kits could be created to leverage the design work already done on the development board when cost-reducing for production.

Leave a Reply

featured blogs
Jan 26, 2023
Are you experienced in using SVA? It's been around for a long time, and it's tempting to think there's nothing new to learn. Have you ever come across situations where SVA can't solve what appears to be a simple problem? What if you wanted to code an assertion that a signal r...
Jan 24, 2023
We explain embedded magnetoresistive random access memory (eMRAM) and its low-power SoC design applications as a non-volatile memory alternative to SRAM & Flash. The post Why Embedded MRAMs Are the Future for Advanced-Node SoCs appeared first on From Silicon To Software...
Jan 19, 2023
Are you having problems adjusting your watch strap or swapping out your watch battery? If so, I am the bearer of glad tidings....
Jan 16, 2023
By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your… ...

featured video

Synopsys 224G & 112G Ethernet PHY IP OIF Interop at ECOC 2022

Sponsored by Synopsys

This Featured Video shows four demonstrations of the Synopsys 224G and 112G Ethernet PHY IP long and medium reach performance, interoperating with third-party channels and SerDes.

Learn More

featured chalk talk

Powering Servers and AI with Ultra-Efficient IPOL Voltage Regulators

Sponsored by Infineon

For today’s networking, telecom, server, and enterprise storage applications, power efficiency and power density are crucial components to the success of their power management. In this episode of Chalk Talk, Amelia Dalton and Dr. Davood Yazdani from Infineon chat about the details of Infineon’s ultra-efficient integrated point of load voltage regulators. Davood and Amelia take a closer look at the operation of these integrated point of load voltage regulators and why using the Infineon OptiMOS 5 FETs combined with the Infineon Fast Constant On Time controller engine make them a great solution for your next design.

Click here for more information about Integrated POL Voltage Regulators