All the FPGA action these days is in the new, emerging markets right? As we’ve all discussed for awhile, CPLDs are a nice steady market with slow growth, and networking apps (the ones that built the FPGA industry to where it is today) took a nose-dive a few years back and are out of favor. … Read More → "Xilinx Goes Retro"

It stands to reason. Some components of system-on-chip design are static. You’re not going back and re-engineering them every two weeks. The multiplier was designed long ago and doesn’t really need to be designed again every time the moon changes phase. Neither does the PCI core, for that matter. They’re both stable and well-debugged. It’s … Read More → "Semi-Programmable"

I  have now attended more than half of the 41 annual Design Automation Conferences. One of the things I’ve noticed during those twenty-odd years is that DAC started at the end of the design flow and moved forward. From the days when the hot topics in design automation were replacing tape and glass with Calma … Read More → "Cool and Groovy at DAC"

The 41st Design Automation Conference in San Diego last week wasn’t a bad conference. In fact, it was quite a good one. According to the program, there were a record number of papers submitted to the technical conference, and the selection panel had to be “more selective than ever” in choosing the elite few that … Read More → "DAC’s Dangerous Undertones"

As suppliers jockey for position in offering products that hit the gap between the flexibility and risk-free design offered by FPGA and the performance and unit-cost advantages of cell-based ASIC, unlikely alliances are inevitable. In this case, ASIC design tool leader Synopsys is teaming with leading FPGA vendor Altera to jointly develop solutions for the … Read More → "Racing for the Gap"

In the 90s, it was obvious that within the decade, exploding gate counts would outstrip our ability to design. The popular debate topic at that time was how the “white space” would be used. “White space” represented the difference between the number of available gates on a semiconductor device, and the number of gates we … Read More → "Virtex-4"

Introduction Galileo Avionica needed an easy-to-use VME BUS monitor that could be used by both hardware and software engineers working on VME-based projects. Using a plug-in VME board with an Altera FPGA, embedded DiaLite virtual instrumentation from Temento Systems, and a TCL/TK-based custom human interface, an innovative solution was crafted that allows simple, multi-use analysis … Read More → "Leveraging On-Chip Debug for VME"

Electronic design automation has its own secret little cold fusion. An innovation that everyone quietly hopes is possible but publicly disavows. A development that would make life beautiful, dogs and cats live happily together, and money grow on trees. This missing link is “behavioral synthesis,” the direct compilation of untimed algorithmic descriptions into practical hardware … Read More → "Catapult C"