feature article
Subscribe Now

Jason Cong

Training Tomorrow's Talent

Professor Jason Cong’s office on the campus of UCLA is full, but not cluttered; important, but not pretentious; functional, but not over-designed. A wall of bookshelves that overlooks the desk and conference table is filled with proceedings from probably every technical conference ever to approach the subject of programmable logic design. One gets the impression that Professor Cong has not only read them all, but also participated in the production of a good percentage of them.

There is nothing in particular here to tip the casual visitor that this is the dojo where much of the best technical talent in the FPGA design tools industry was trained. There are no signs or scoreboards proclaiming the number of graduates that are now working at companies like Altera, Xilinx, Cadence, Magma, Mentor and others. Their legacy can be felt here, though, in the new generation of students that are now studying, learning, and innovating — working to earn their right to join the ranks of engineers that define the direction of this pivotal technology.

Jason was born and raised in China. From an early age, he had a gift and an enthusiasm for mathematics. In his native China, he was regularly winning math competitions, and through those competitions, he earned his first opportunity to visit the United States. In 1980, (shortly after China and the US normalized relationships in 1979), he was invited to travel to the US to compete in the International Math Olympics. Unfortunately, following the defection of a young tennis player, China closed the doors and cancelled all cultural exchanges so the trip was called off.

Jason attended the prestigious Peking University in 1981, where he studied computer science, but still maintained a strong interest in mathematics. Once China began allowing travel to the US again, Jason applied to several US universities for graduate studies and took a fellowship to study computer science at the University of Illinois at Urbana-Champaign with Professor David Liu, where he earned his Masters degree and Ph.D. “David Liu was a perfect match for me,” comments Professor Cong. “He was looking for ways to apply combinatorial mathematics and was looking at VLSI design. I was extremely interested in discrete optimization algorithms like sorting and graph matching, which turned out to be very useful for the early work there.”

Initially, Cong looked at VLSI design as just an interesting application of mathematics. “I didn’t think much about the topic at the time,” he continues. “I was looking at the methods of applying mathematics and the use was secondary.” As Cong’s experience grew, so did his interest in the topic of design automation. During this time, Cong connected with Brian Preas at Xerox PARC, where he began to apply his skills to research on global routing algorithms. At that time, he was first faced with the question that would repeat itself throughout his career: whether to go into the comparatively lucrative commercial sector or to remain in academia and help future generations of engineers.

“Dave Liu was a great mentor and ultimately influenced me to give back to the system that had given so much to me,” said Cong. “Deep in my heart, I’m an engineer and want to build things, but I have a great appreciation for the education system and want to help support and perpetuate that.” After graduating in 1990, he went to UCLA to teach. “I was born in Beijing and wanted to live somewhere with a great location and a big city,” Cong continues. “I really liked UCLA for that, and it was an excellent school where I felt I could be successful.”

The first problems Professor Cong tackled were in the area of VLSI physical design, focusing in a new area of interconnect optimization, addressing problems like interconnect topology generation, buffer placement, and wire sizing. Over time, he also wanted to carry over into logic synthesis, as he felt that the two areas were highly interrelated. “I began to read papers on FPGA design and saw a huge opportunity for development,” Cong recalls. “I split my research program into two parts: one focused on interconnect, and the other on FPGA.”

The FPGA focus soon met with significant success. “The FlowMap algorithm that was invented here won a 1994 IEEE Circuit & Systems Society best paper award,” says Cong. “The algorithm gave a guaranteed depth-optimal mapping solution in polynomial time for look up table (LUT) -based FPGAs. It was exciting to know that there were still problems where an efficient algorithm could be applied to achieve known optimality.” Such success stimulated significant commercial interest in supporting research and development on the topic, and a number of FPGA vendors hopped on board, giving funding to the project.

Once the FlowMap algorithm can provide an optimal mapping solution for any K-input LUT- based FPGAs, a natural question follows: “What should K be?” This led to research on tools that would evaluate architectural options for new FPGA development. By the late 1990s, there were two strong FPGA-related research threads going on in Cong’s department. First was the continuation of the architectural evaluation technology, and second was technology to optimize synthesis and mapping together. In 1998 Cong founded APlus Design Technologies as a commercial entity to create and market tools for physical synthesis of FPGAs. Along with partners that included two former Ph.D. students and a researcher from Intel, APlus created product-quality tools for commercial use to evaluate potential FPGA architectures and to optimize FPGA designs by combining logic and physical optimization. “Physical synthesis was a natural fit for the challenges faced by the FPGA design community,” says Cong.

The first APlus customers saw significant advantages to using the technology, and FPGA vendors were fast to show interest. The company built its base on OEM agreements with vendors instead of developing its own sales force and grew steadily to over 20 employees as strictly a technology company. “We never had venture funding. We were a technology-driven company from day one,” recalls Cong. “We had a strong and inspired team with zero turnover. We didn’t even add our first sales or marketing until the end of the third year.”

One year after their launch, APlus also started offshore development in China. “I worked with my undergraduate connections in China to set up a mutually beneficial development arrangement,” says Cong. “Once we did the work to get it up and running, it worked great.” The multi-national development accelerated progress on the tools, and the company was soon at a juncture where it needed to cope with its own growth.

“Since we had a multi-vendor tool, acquisition by a single FPGA vendor didn’t make the most sense,” says Cong. “We eventually arrived at an agreement with Magma Design Automation to acquire the company in June 2003. I was very much attracted by the vision of Rajeev Madhavan (Magma Chairman and CEO) of building a unified RTL to GDS flow to support all silicon implementation platforms, including standard cell designs, FPGAs, and emerging structured ASICs.” One year after acquisition, that vision has played out very well, and sales of new products resulting from Aplus acquisition has exceeded Cong’s expectations. Cong sees the company as a case study in how academic/industrial partnerships can succeed in developing and introducing technology to the commercial market.

After staying with Magma for one year, Professor Cong continues in an advisory position as the Chief Technology Advisor with Magma, but he has returned to his first passion, educating the engineers of tomorrow, as his primary vocation. “I think there are many more interesting and challenging problems yet to be solved,” says Cong. “For example, the introduction of processors into FPGA design creates opportunities for hardware/software co-design, and rapid increase in design complexity requires raising the level of design abstraction without losing touch with the physical realities of the architecture. There are essentially no tools available in this space today. Power is also a big problem that needs to be addressed with the latest generation devices.”

As more problems emerge, it’s good to know that Professor Jason Cong is out there thinking about them and bringing to life a new generation of technologists inspired by the vision of this modern-day luminary. It’s easy to remember that behind every new technological advance is a group of inspired, talented engineers. It also pays to remember that behind every group of engineers is a master educator and guide like Jason Cong developing the knowledge, skills, and work ethic that ultimately drive them to their successes.

Leave a Reply

featured blogs
Apr 16, 2024
In today's semiconductor era, every minute, you always look for the opportunity to enhance your skills and learning growth and want to keep up to date with the technology. This could mean you would also like to get hold of the small concepts behind the complex chip desig...
Apr 11, 2024
See how Achronix used our physical verification tools to accelerate the SoC design and verification flow, boosting chip design productivity w/ cloud-based EDA.The post Achronix Achieves 5X Faster Physical Verification for Full SoC Within Budget with Synopsys Cloud appeared ...
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

Using the Vishay IHLE® to Mitigate Radiated EMI
Sponsored by Mouser Electronics and Vishay
EMI mitigation is an important design concern for a lot of different electronic systems designs. In this episode of Chalk Talk, Amelia Dalton and Tim Shafer from Vishay explore how Vishay’s IHLE power inductors can reduce radiated EMI. They also examine how the composition of these inductors can support the mitigation of EMI and how you can get started using Vishay’s IHLE® High Current Inductors in your next design.
Dec 4, 2023