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Making the Line Move Faster

No one likes standing in line, but if you’re going to be doing any serious parallel processing, you’ll run into many queues as a way for threads or processes to send messages to each other. Usually they’re implemented in software, which adds a level of overhead to the programs, in particular when putting things on or taking them off the queue.

For instance, when putting a new item into the queue, you have to check to see if there is room in the queue, and you have to upgrade the head … Read More → "Making the Line Move Faster"

Par for the Course

In the forum thread about Altium’s move to China, I was asked to comment on the “negative” aspects of the EDA space in general, and how that relates to Altium’s situation.  We certainly don’t want to come off as “Pollyanna Engineering Journal,” so here goes.

First, as to why we write so frequently about Altium – it is because they make a lot of aggressive strategy moves.  Aggressive moves – whether they’re good or … Read More → "Par for the Course"

Go Wide

Last week Cadence announced a new wide-I/O memory controller IP block, ostensibly the first of its kind. This actually represents a risk start based on a JEDEC standard that’s not yet complete.

The idea behind the wide-I/O movement is predicated on use in 3D ICs, where a memory chip will be stacked on a logic chip, with the connections being made by TSVs</ … Read More → "Go Wide"

Dude, That’s So Random

Many of us grew up knowing that you can’t have truly random numbers in your algorithms or circuits. The best you can do is “pseudo-random,” which means take a non-random number and shake it up really hard so it looks random. But… if you start with the same number every time, then you’ll end up with the same sequence every time.

Oh yeah, that’s the other thing: pseudo-random number generators (PNRGs) are all about sequences. You seed the thing with a value, and, from then on, it supplies … Read More → "Dude, That’s So Random"

TSMC Going for the Whole Package

It looks like the chip packaging industry may be getting a new competitor.

I spent a few minutes with TSMC’s Sr. VP for R&D Shang-yi Chiang last week at the TSMC Symposium to follow up on one of the topics he had raised in his presentation, that of low-K dielectrics and some of the impact they were having.

For those of us not as deeply steeped in this stuff, it’s easy to get confused by low-K and high-K, since they are both trumpeted as important new developments. High-K is … Read More → "TSMC Going for the Whole Package"

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Aug 20, 2019
PCB design is like conducting a full-fledged orchestra. In many creation myths, a supreme being sings the world into existence - take the fourteen Ainurs of Lord of the Rings, for example. Well,... [[ Click on the title to access the full blog on the Cadence Community site. ...
Aug 19, 2019
In this new video, Samtec’s Kevin Burt introduces Samtec Direct Connect'„¢. Direct Connect gives the benefit of exiting a higher number of lanes at low loss from the chip package, which can be very useful in both high performance computing and network switching applic...