editor's blog
Subscribe Now

Go Wide

Last week Cadence announced a new wide-I/O memory controller IP block, ostensibly the first of its kind. This actually represents a risk start based on a JEDEC standard that’s not yet complete.

The idea behind the wide-I/O movement is predicated on use in 3D ICs, where a memory chip will be stacked on a logic chip, with the connections being made by TSVs. Instead of requiring higher-drive I/Os that connect to chip pads and traverse PCB traces to get to a memory chip (or back from the memory chip), you stay entirely within the package. An array of TSVs mean that you can handle far more I/Os that if you have to go to package pins. And the drive requirements are reduced tremendously, reducing both the size (due to smaller transistors) and power of the resulting combination.

Of course, with more connections, you get much higher bandwidth: this is a 512-bit interface. That’s a lot more data available in one chunk than you can traditionally get.

Cadence’s controller block includes traffic shaping algorithms to increase throughput as well as features to address power, including traffic sensing (so that power can respond to traffic) and an option for dynamic voltage and frequency scaling (DVFS).

This would seem to come well ahead of the standard, which is projected (no promises!) to be available to non-members in September. But, in many such standardization cases, the technical details are approved first, and then the resulting standard goes through a higher-level board approval step that largely examines the process by which the standard was set to make sure that it was done properly. 

Clearly Cadence is betting that there will be no further technical changes. Or that, if there are, they can update the IP before any customer commits to final silicon.

Leave a Reply

featured blogs
Dec 8, 2022
The automotive industry is shifting its focus to reducing CO2 emissions from its vehicles, and it's no surprise, given the current state of the environment. Renault is a world leader in the automotive market, working on internal combustion engines, hybrid engines, electric ve...
Dec 8, 2022
Is the world ready for the next transubstantiation of encabulation?...
Dec 8, 2022
Explore what it means for semiconductor IP companies to offer ASIC-like chip design services and learn how turnkey IP solutions ease the SoC design flow. The post What It Means for an IP Vendor to Offer ASIC-Like Services appeared first on From Silicon To Software....
Dec 7, 2022
By Karen Chow When Infineon needed to select a field solver for the development of their next-generation power semiconductor products,… ...

featured video

TI isolation technology: Different by design

Sponsored by Texas Instruments

The need for isolation is growing, and while electromechanical relays, optocouplers and discrete transformers have been widely adopted for signal and power isolation, we're committed to pushing isolation technology further. See where we’re taking our capacitive and magnetic technologies next.

Learn More

featured chalk talk

The Composite Power Inductance Story

Sponsored by Mouser Electronics and Vishay

Power inductor technology has made a huge difference in the evolution of our electronic system designs. In this episode of Chalk Talk, Amelia Dalton chats with Tim Shafer from Vishay about the history of power inductor technology, how Vishay developed the most compact and efficient power inductor on the market today and why Vishay’s extensive portfolio of composite power inductors might be the best solution for your next embedded system design.

Click here for more information about Vishay Inductors