editor's blog

Dude, That’s So Random

Many of us grew up knowing that you can’t have truly random numbers in your algorithms or circuits. The best you can do is “pseudo-random,” which means take a non-random number and shake it up really hard so it looks random. But… if you start with the same number every time, then you’ll end up with the same sequence every time.

Oh yeah, that’s the other thing: pseudo-random number generators (PNRGs) are all about sequences. You seed the thing with a value, and, from then on, it supplies a stream of numbers in an unpredictable (for practical purposes) fashion like a Pez dispenser where you don’t know what color is going to come up next.

So it’s all about the seed, and it’s been very hard to produce seeds that are truly random.

Actually, there’s even a problem with the concept of “truly random”: it’s not that simple. If you have an 8-bit field that unpredictably generates one of 5 values, well, that’s kind of random. But you could be generating one of 256 values to make full use of the 8 bits. Such a scheme would be said to have low entropy; most of the 8 bits aren’t, in fact, random at all.

We looked at some aspects of hardware randomness in our article on physically unclonable functions (PUFs) a few months back. One of the companies we covered, Intrinsic ID, has just announced a new random number generator, iRNG, based on the technology they use for their PUF. It makes use of the noise inherent in the power-up of SRAM bits.

If you look at their basic drawing, they have a conditioned “true random seed” coming from their “entropy source” that feeds a DRBG, which stands for “deterministic random bitstream generator.” And if you go to Wikipedia and look that up, it takes you to the page for PRNGs. In other words, a DRBG is another name for a PRNG. And I can totally understand how they would not want the phrase “pseudo-random” showing up anywhere in marketing materials that are trying to convey a message of “true” randomness.

However, this is simply a case of the PRNG we’ve been talking about, only now fed by a seed that they say is truly random. Of course, since there’s no such thing as “truly” random, then how random is it? They claim “high entropy” (and they can probably quantify that for a given technology). But we can get a sense from thinking about the underlying mechanism.

An SRAM bit is more or less a bistable element that, in the extreme, is very well balanced so that, as it’s powering up in a perfectly noiseless environment, it would have an equal chance of toppling over into a 1 state or a 0 state. The opposite extreme can be seen in flip-flops that have been explicitly biased to come up in a predictable state by intentionally unbalancing things.

Real SRAM cells, even if designed perfectly, won’t be perfect due to process variations. Intrisic ID uses a 2-kbit memory; each of those bits will be ever so slightly different. Some will be subtly biased to come up 0, some to come up 1. Each chip will be different, so you certainly have a situation where no two systems will behave alike.

If the power-up conditions were perfect and noiseless, then each of these systems would come up the same way each time except for those bits that happened to be perfectly poised – giving you some level of non-zero entropy.

But noiseless is impossible. (At some point I assume even quantum fluctuations would play a part.) So high entropy comes in if the noise available is high enough – and unpredictable enough – that even those bits subtly biased in one direction or another can still be pushed over to the other side. Instead of a 50/50 chance of a 1 or 0, perhaps you’ve got a 70/30 chance.

So, just as the 5-value randomness didn’t make complete use of an 8-bit field above, here also, the entropy you get won’t make use of the full 2-kbit field. But if you’re getting a good percentage of those bits to be random, well, that’s still a pretty wide field.

So the key to the Intrinsic ID is this SRAM plus the conditioning; the DRBG/PRNG is designed to meet the requirements of various security standards. SRAM aside, this is available as hardware or software IP.

featured blogs
Sep 11, 2024
In which we cogitate, ruminate, and pontificate on the things you can do to further your goal of landing (and keeping) a job in engineering...

A game-changer for IP designers: design-stage verification

Sponsored by Siemens Digital Industries Software

In this new technical paper, youâ€™ll gain valuable insights into how, by moving physical verification earlier in the IP design flow, you can locate and correct design errors sooner, reducing costs and getting complex designs to market faster. Dive into the challenges of hard, soft and custom IP creation, and learn how to run targeted, real-time or on-demand physical verification with precision, earlier in the layout process.

featured chalk talk

Developing a Secured Matter Device with the OPTIGAâ„˘ Trust M MTR Shield
Sponsored by Mouser Electronics and Infineon
In this episode of Chalk Talk, Amelia Dalton and Johannes Koblbauer from Infineon explore how you can add Matter and security to your next smart home project with the OPTIGAâ„˘ Trust M MTR shield. They also investigate the steps involved in the OPTIGAâ„˘ Trust M Matter design process, the details of the OPTIGAâ„˘ Trust M Matter evaluation board and how you can get started on your next Matter IoT device.
Jul 2, 2024
15,335 views