editor's blog
Subscribe Now

Dude, That’s So Random

Many of us grew up knowing that you can’t have truly random numbers in your algorithms or circuits. The best you can do is “pseudo-random,” which means take a non-random number and shake it up really hard so it looks random. But… if you start with the same number every time, then you’ll end up with the same sequence every time.

Oh yeah, that’s the other thing: pseudo-random number generators (PNRGs) are all about sequences. You seed the thing with a value, and, from then on, it supplies a stream of numbers in an unpredictable (for practical purposes) fashion like a Pez dispenser where you don’t know what color is going to come up next.

So it’s all about the seed, and it’s been very hard to produce seeds that are truly random.

Actually, there’s even a problem with the concept of “truly random”: it’s not that simple. If you have an 8-bit field that unpredictably generates one of 5 values, well, that’s kind of random. But you could be generating one of 256 values to make full use of the 8 bits. Such a scheme would be said to have low entropy; most of the 8 bits aren’t, in fact, random at all.

We looked at some aspects of hardware randomness in our article on physically unclonable functions (PUFs) a few months back. One of the companies we covered, Intrinsic ID, has just announced a new random number generator, iRNG, based on the technology they use for their PUF. It makes use of the noise inherent in the power-up of SRAM bits.

If you look at their basic drawing, they have a conditioned “true random seed” coming from their “entropy source” that feeds a DRBG, which stands for “deterministic random bitstream generator.” And if you go to Wikipedia and look that up, it takes you to the page for PRNGs. In other words, a DRBG is another name for a PRNG. And I can totally understand how they would not want the phrase “pseudo-random” showing up anywhere in marketing materials that are trying to convey a message of “true” randomness.

However, this is simply a case of the PRNG we’ve been talking about, only now fed by a seed that they say is truly random. Of course, since there’s no such thing as “truly” random, then how random is it? They claim “high entropy” (and they can probably quantify that for a given technology). But we can get a sense from thinking about the underlying mechanism.

An SRAM bit is more or less a bistable element that, in the extreme, is very well balanced so that, as it’s powering up in a perfectly noiseless environment, it would have an equal chance of toppling over into a 1 state or a 0 state. The opposite extreme can be seen in flip-flops that have been explicitly biased to come up in a predictable state by intentionally unbalancing things.

Real SRAM cells, even if designed perfectly, won’t be perfect due to process variations. Intrisic ID uses a 2-kbit memory; each of those bits will be ever so slightly different. Some will be subtly biased to come up 0, some to come up 1. Each chip will be different, so you certainly have a situation where no two systems will behave alike.

If the power-up conditions were perfect and noiseless, then each of these systems would come up the same way each time except for those bits that happened to be perfectly poised – giving you some level of non-zero entropy.

But noiseless is impossible. (At some point I assume even quantum fluctuations would play a part.) So high entropy comes in if the noise available is high enough – and unpredictable enough – that even those bits subtly biased in one direction or another can still be pushed over to the other side. Instead of a 50/50 chance of a 1 or 0, perhaps you’ve got a 70/30 chance.

So, just as the 5-value randomness didn’t make complete use of an 8-bit field above, here also, the entropy you get won’t make use of the full 2-kbit field. But if you’re getting a good percentage of those bits to be random, well, that’s still a pretty wide field.

So the key to the Intrinsic ID is this SRAM plus the conditioning; the DRBG/PRNG is designed to meet the requirements of various security standards. SRAM aside, this is available as hardware or software IP.

More info in the release

Leave a Reply

featured blogs
Sep 21, 2021
Learn how our high-performance FPGA prototyping tools enable RTL debug for chip validation teams, eliminating simulation/emulation during hardware debugging. The post High Debug Productivity Is the FPGA Prototyping Game Changer: Part 1 appeared first on From Silicon To Softw...
Sep 20, 2021
As it seems to be becoming a (bad) habit, This Week in CFD is presented here as Last Week in CFD. But that doesn't make the news any less relevant. Great article on wind tunnels because they go... [[ Click on the title to access the full blog on the Cadence Community si...
Sep 18, 2021
Projects with a steampunk look-and-feel incorporate retro-futuristic technology and aesthetics inspired by 19th-century industrial steam-powered machinery....
Aug 5, 2021
Megh Computing's Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization   Because Megh's ...

featured video

Silicon Lifecycle Management Paradigm Shift

Sponsored by Synopsys

An end-to-end platform solution, Silicon Lifecycle Management leverages existing, mature, world-class technologies within Synopsys. This exciting new concept will revolutionize the semiconductor industry and how we manage silicon design. For the first time, designers can look inside silicon chip devices from the moment the design is created to the point at which they end their life.

Click here to learn more about Silicon Lifecycle Management

featured paper

Keep Your System Up and Running With a Single Supercapacitor

Sponsored by Maxim Integrated (now part of Analog Devices)

This design solution presents a novel solution for backing up system power in both battery and line-powered systems. The elegant architecture runs from a single supercapacitor, provides a tightly regulated 5V output at up to 3A, and features 94% efficiency.

Click to read more

featured chalk talk

Just 1-Wire to Power and Operate I2C or SPI Endpoints

Sponsored by Mouser Electronics and Maxim Integrated (now part of Analog Devices)

If you are working on a connection or IO constrained design, a one wire solution could be a great way for you to power and operate your I2C or SPI endpoints. In this episode of Chalk Talk, Amelia Dalton chats with Scott Jones from Maxim Integrated about the DS28E18 communications bridge: a one wire solution that can help you address a variety of system level challenges including protocol conversion, wiring limitations, and communication distance concerns.

Click here for more information about the Maxim Integrated DS28E18EVKIT Evaluation System