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TSMC Going for the Whole Package

It looks like the chip packaging industry may be getting a new competitor.

I spent a few minutes with TSMC’s Sr. VP for R&D Shang-yi Chiang last week at the TSMC Symposium to follow up on one of the topics he had raised in his presentation, that of low-K dielectrics and some of the impact they were having.

For those of us not as deeply steeped in this stuff, it’s easy to get confused by low-K and high-K, since they are both trumpeted as important new developments. High-K is for the gate, where you want good coupling; low-K is for the dielectric between interconnect layers, where you want to minimize coupling, which is increasingly harder due to the incredibly thin dimensions we’re seeing.

It turns out that air is pretty much the gold standard for low K. And your standard chip dielectrics are decidedly not air. So TSMC approximates air by creating a matrix of tiny bubbles – essentially turning the dielectric into a high-tech Styrofoam. 

They do this by mixing in an organic ingredient; a higher-temp bake burns off the material, leaving voids. They also add some carbon to the overall mix to improve the structural integrity of what remains.

Problem is, this makes the material much more brittle, and it doesn’t stick as well to the layer below it. This is exacerbated by the material having a different thermal coefficient than the molding compound used for packaging; all of this hurts reliability.

So TSMC believes that they need to get more involved with the packaging themselves, in particular through the use of multi-chip constructs like 3D ICs or with silicon interposers. 

And they’re not talking about partnering with a packaging house. They want to do it themselves.

The existing packaging business has margins too low to be of interest to them. So they want to develop their own technology (not acquire it) to improve the margins. 

R&D is just starting.

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