On the heels of their Verdi3 announcement, Springsoft continues its triplication, now with Laker3. They position Laker as the “best established interoperable custom design flow.” As with all carefully-crafted positioning statements, the key qualifier they use here is “interoperable.” This refers both to the fact that they use the OpenAccess database and to their ability to integrate with Mentor’s RealTime engine for on-the-fly … Read More → "Another 3 from Springsoft"
It’s kind of a given these days that any major software project will contain more than just homegrown code. At the very least, it’s likely to have open-source bits and pieces in there. It’s Protecode’s business to provide tools to companies so that they can manage their code and know all of the licensing obligations and security issues.
But what if you’re a small company and, for instance, someone is looking at investing or … Read More → "Software Pedigree Check for Small Companies"
Back when discussion CMOS-compatible MEMS, I briefly mentioned a couple tools from Coventor that are used in MEMS design. But one of them actually has use for any semiconductor process. You might think it’s another TCAD tool, but actually, it isn’t.
TCAD tools work with low-level physics to model small portions of an overall process. It’s like using SPICE to simulate a cell – very detailed, but can& … Read More → "Simulating the Whole Process"
I got introduced to Electric Cloud at ESC. They make software automation tools, with a focus on build automation and build acceleration.
The build flow is managed by ElectricCommander, which ties into the IDE and has hooks for the actual tools being summoned during the build process. The idea is that it’s easier and faster to manage the flow this way than by managing complex scripts. They have recently added the ability to define the flows graphically rather than through a form, making the process easier and more intuitive.
ElectricAccelerator can be used … Read More → "Better Software Builds"
There’s technology and then there’s marketing. Properly done, they work well together. But there are times when the marketing gets ahead of the technology and times when it can actually be behind the technology. In both cases, it can be intentional or inadvertent.
We’ve talked about the META processor from Imagination Technologies (IMG), both generically and with respect to its threading capabilities. Still, IMG have intentionally focused their messaging on the … Read More → "Exploiting the IoT"
As Jim Turley mentioned in his ESC run-down, Express Logic has done a deal with IAR to make available a “lite” version of the ThreadX operating system. Of course the features are cut back, as he explains. But it was the nature of the licensing that caught my attention.
Full-up ThreadX is licensed by project: when you finish the project, you’re done with that license, and you buy a new one when a new project starts up. While this model works for larger … Read More → "Is an OS More Like IP or a Tool?"
We recently heard Netronome’s view on next-generation firewalls, and in particular, how they are migrating from the more traditional boundary protection to be distributed throughout compute farms on each rack.
Well, it goes beyond that, at least in Icon Labs’ view; I talked with them at ESC (or Design West, or ESC, a subsidiary of Design West). They point out the fact that embedded systems are all becoming hackable, with a few interesting examples:
At last week’s SNUG, I had a chat with Uri Tal, CEO of startup Rocketick, about their simulation acceleration technology. What they do bears some resemblance to the parallelization semi-automation done by Vector Fabrics or the exploration done by CriticalBlue, except that here it’s working with Verilog instead of C and it’s fully automated and transparent to the user. He claims they can accelerate simulation by over 10X.
They use a GPU to achieve this kind of parallelization. This has promise … Read More → "Faster Simulation on GPUs"
DDR memory timing is tricky business. Especially with later versions of the standard, the timing for each memory on a module has to be carefully determined; there’s no such thing as just issuing a read or write to all the chips together. A further problem, however, is that the timing is subject to change based on a number of factors, including environmental conditions and wear-out.
Some companies address this by doing a power-up calibration that involves reading and writing to figure out the optimal timing. But things can still drift as the system warms up … Read More → "Keeping DDR Performance Fresh"
There’s lots of talk about 3D (and 2-1/2-D) ICs, with through-silicon vias (TSVs) being a key enabling technology. The possibilities are exciting, but the reality also appears to be challenging. Costs are high, there are still reliability questions to answer, and the overall design flow has yet to be thoroughly established. Even just simple questions like place and route have been the subject of early projects (involving at least one company that’s no longer in business).
Synopsys has recently announced their 3D-IC … Read More → "3D IC Design Suite"
