There’s lots of talk about 3D (and 2-1/2-D) ICs, with through-silicon vias (TSVs) being a key enabling technology. The possibilities are exciting, but the reality also appears to be challenging. Costs are high, there are still reliability questions to answer, and the overall design flow has yet to be thoroughly established. Even just simple questions like place and route have been the subject of early projects (involving at least one company that’s no longer in business).

Synopsys has recently announced their 3D-IC Initiative, essentially a collection of their EDA tools focused on hacking a flow through this technology jungle. It includes digital and custom design support, test, parasitic extraction, memory compilation, simulation, and more. All of which are impacted by 3D IC design.

Even though you might wonder, “How hard can it be to stack one die on top of another?” the answer appears to be, “Pretty hard.” At least until the tools settle down to make it easier.

More details in their release…