editor's blog
Subscribe Now

Keeping DDR Performance Fresh

DDR memory timing is tricky business. Especially with later versions of the standard, the timing for each memory on a module has to be carefully determined; there’s no such thing as just issuing a read or write to all the chips together. A further problem, however, is that the timing is subject to change based on a number of factors, including environmental conditions and wear-out.

Some companies address this by doing a power-up calibration that involves reading and writing to figure out the optimal timing. But things can still drift as the system warms up or the box gets moved into the sun or the environment changes for any of a number of other reasons.

Uniquify, a company whose business has morphed from ASIC design services into an IP company (with further evolution underway) has earned a patent on dynamic recalibration – the ability to keep tuning the timing during use. The prior barrier had been the fact that writing to the memory for calibration purposes is destructive. That’s not a problem at startup, before anyone has started using memory, but while the system is running, the application has control of the memory, and there is little appetite for setting a bit of it aside for use only by calibration.

Uniquify’s approach was to use application memory, but copy and store the current contents of the calibration location, do the calibration, and then replace the contents so that the application never notices it missing. The timing of this recalibration can be set to coincide with refresh or at some other designer-defined interval.

The calibration looks both for drift in the timing window as well as changes to the width of that window. Each recalibration finds the edges of the window and recenters the strobe. But if the window closes, then a specific error is flagged.

You can find out more in their latest release.

Leave a Reply

featured blogs
Jul 2, 2020
Using the bitwise operators in general, and employing them to perform masking operations in particular, can be extremely efficacious....
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...
Jun 26, 2020
[From the last episode: We looked at the common machine-vision application and its primary .] We'€™ve seen that vision is a common AI these days, and we'€™ve also talked about the fact that our current spate of neural networks are not neuromorphic '€“ that is, they'€™...

Featured Video

Product Update: New DesignWare® IOs

Sponsored by Synopsys

Join Faisal Goriawalla for an update on Synopsys’ DesignWare GPIO and Specialty IO IP, including LVDS, I2C and I3C. The IO portfolio is silicon-proven across a range of foundries and process nodes, and is ready for your next SoC design.

Click here for more information about DesignWare Embedded Memories, Logic Libraries and Test Videos

Featured Paper

Cryptography: A Closer Look at the Algorithms

Sponsored by Maxim Integrated

Get more details about how cryptographic algorithms are implemented and how an asymmetric key algorithm can be used to exchange a shared private key.

Click here to download the whitepaper

Featured Chalk Talk

Cloud Computing for Electronic Design (Are We There Yet?)

Sponsored by Cadence Design Systems

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

More information about the Cadence Cloud Portfolio