editor's blog
Subscribe Now

Not All Logic Stages Need to Be Equal

I had a conversation with Cadence at ARM TechCon, and one of the things they’re talking about is what they call clock/data co-optimization as an alternative to traditional synchronous logic optimization.

Typically, designers work hard to make sure each logic stage in the overall logic pipeline can be implemented in the time required before the next clock arrives. Some stages have more logic than others, and you have to spend more time on those ones to get the speed right.

Meanwhile, someone spends a lot of effort synthesizing a clock tree that’s balanced and homogeneous and gets a strobe to each register at the same time.

But Cadence’s point is, it doesn’t have to be that way. What if you borrowed from the easy logic stages to cut the hard logic stages more slack? Then the clock could arrive a bit early at the hard logic stage so that it would have more time to get the hard logic done. You might be able to use smaller or fewer buffers, reducing logic and power.

This means that different stages may have different delays, and, most unconventionally, that clocks might arrive at different times in different places. (Which actually isn’t such a bad thing from an EMI standpoint.)

By doing this, they found that a particular ARM A9 design gained 40 MHz of performance while lowering dynamic power by 10.4% and clock area (and hence leakage) by 31%. A complete win win.

Leave a Reply

featured blogs
May 29, 2022
https://youtu.be/2F6MIuGFcHA Made in my Mini Cooper Convertible Monday: Embedded Vision Summit 2022 Tuesday: May Update: ACM Digital Library, Open RAN Security, Framework Laptop Upgrade, Malcolm... ...
May 26, 2022
Introducing Synopsys Learning Center, an online, on-demand library of self-paced training modules, webinars, and labs designed for both new & experienced users. The post New Synopsys Learning Center Makes Training Easier and More Accessible appeared first on From Silico...
May 25, 2022
There are so many cool STEM (science, technology, engineering, and math) toys available these days, and I want them all!...
May 24, 2022
By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely… ...

featured video

Increasing Semiconductor Predictability in an Unpredictable World

Sponsored by Synopsys

SLM presents significant value-driven opportunities for assessing the reliability and resilience of silicon devices, from data gathered during design, manufacture, test, and in-field. Silicon data driven analytics provide new actionable insights to address the challenges posed to large scale silicon designs.

Learn More

featured paper

Intel Agilex FPGAs Deliver Game-Changing Flexibility & Agility for the Data-Centric World

Sponsored by Intel

The new Intel® Agilex™ FPGA is more than the latest programmable logic offering—it brings together revolutionary innovation in multiple areas of Intel technology leadership to create new opportunities to derive value and meaning from this transformation from edge to data center. Want to know more? Start with this white paper.

Click to read more

featured chalk talk

10X Faster Analog Simulation with PrimeSim Continuum

Sponsored by Synopsys

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Click to read more about PrimeSim Continuum