Xilinx has a new challenge on their hands. It’s called “software.” And at ARM TechCon, they announced their software enablement initiative for Zynq.
Of course, this is the same challenge any SoC project has. And SoC designers have a variety of tools to help with this, from virtual platforms to emulators. These allow software development to get up and running before the actual silicon is available.
What’s new is that Xilinx has their spiffy new Zynq family featuring the ARM Cortex A9 MPcore – one or more copies. And it’s just itching to run some software. And so they should naturally be able to take advantage of the infrastructure that’s there for SoCs.
Except for one thing: SoC tools cost money. FPGA tools don’t.
OK, technically, they do cost money… but no one pays. (What? You actually paid? Hahahahahaha…)
So… getting FPGA users to pay SoC bucks for tools is a tough sell.
Instead, Xilinx announced two things it’s trying in order to help out.
On one front, they’re actually trying not to market Zynq so much as an FPGA: instead, it’s a processor platform with some configurable logic on there. Nope, not an FPGA at all.
On the other front, amongst other components of the toolchain, they’ve made three flavors of virtual platform available, in conjunction with Cadence and Imperas.
For the thrifty open-source types, they’ve got a QEMU offering. The next rung up is for software developers getting their software to work on a fixed configuration. They call this the Zynq-7000 EPP – Software Developer Bundle.
The top-of-the-line is for those tasked with developing the platform model that those software developers will use: This is the Zynq-7000 EPP – System Creator Bundle.
The difference is that those last guys can play with the platform architecture, adding and removing models. The mid-range bundle has a fixed configuration; you can only develop software on it.
Cadence involvement comes through the virtual platform itself and most of the peripheral models. The A9 model comes via Imperas (a fact not public as of the ARM TechCon discussion, but subsequently revealed).
You can find more information on the Xilinx site…
