editor's blog
Subscribe Now

Virtual Platforms for a Non-FPGA

Xilinx has a new challenge on their hands. It’s called “software.” And at ARM TechCon, they announced their software enablement initiative for Zynq.

Of course, this is the same challenge any SoC project has. And SoC designers have a variety of tools to help with this, from virtual platforms to emulators. These allow software development to get up and running before the actual silicon is available.

What’s new is that Xilinx has their spiffy new Zynq family featuring the ARM Cortex A9 MPcore – one or more copies. And it’s just itching to run some software. And so they should naturally be able to take advantage of the infrastructure that’s there for SoCs.

Except for one thing: SoC tools cost money. FPGA tools don’t.

OK, technically, they do cost money… but no one pays. (What? You actually paid? Hahahahahaha…)

So… getting FPGA users to pay SoC bucks for tools is a tough sell.

Instead, Xilinx announced two things it’s trying in order to help out.

On one front, they’re actually trying not to market Zynq so much as an FPGA: instead, it’s a processor platform with some configurable logic on there. Nope, not an FPGA at all.

On the other front, amongst other components of the toolchain, they’ve made three flavors of virtual platform available, in conjunction with Cadence and Imperas.

For the thrifty open-source types, they’ve got a QEMU offering. The next rung up is for software developers getting their software to work on a fixed configuration. They call this the Zynq-7000 EPP – Software Developer Bundle.

The top-of-the-line is for those tasked with developing the platform model that those software developers will use: This is the Zynq-7000 EPP – System Creator Bundle.

The difference is that those last guys can play with the platform architecture, adding and removing models. The mid-range bundle has a fixed configuration; you can only develop software on it.

Cadence involvement comes through the virtual platform itself and most of the peripheral models. The A9 model comes via Imperas (a fact not public as of the ARM TechCon discussion, but subsequently revealed).

You can find more information on the Xilinx site

Leave a Reply

featured blogs
May 22, 2020
As small as a postage stamp, the Seeeduino XIAO boasts a 32-bit Arm Cortex-M0+ processor running at 48 MHz with 256 KB of flash memory and 32 KB of SRAM....
May 22, 2020
Movies have the BAFTAs and Academy Awards. Music has the GRAMMYs. Broadway has the Tonys. Global footballers have the Ballon d’Or. SI/PI engineers have the DesignCon 2020 Best Paper Award? Really? What’s that? Many people are familiar with annual awards mentioned....
May 22, 2020
[From the last episode: We looked at the complexities of cache in a multicore processor.] OK, time for a breather and for some review. We'€™ve taken quite the tour of computing, both in an IoT device (or even a laptop) and in the cloud. Here are some basic things we looked ...
May 21, 2020
In this time of financial uncertainty, a yield-shield portfolio can protect your investments from market volatility.  Uncertainty can be defined as a quantitative measurement of variability in the data [1]. The more the variability in the data – whet...

Featured Video

Featured Paper

Energy-Saving Piezo Haptic Driver is the Touch Sensor's Best Friend

Sponsored by Maxim Integrated

Haptic sensing technology, with its ability to render complex tactile experiences, is becoming popular in portable applications. Excessive power dissipation is a concern with current piezo haptic drivers' implementations. Although the piezoelectric actuator represents a capacitive load, considerable power is dissipated to drive it. This design solution reviews the shortcomings of current piezo haptic driver implementations and introduces a novel, regenerative, boost converter-based implementation that minimizes power dissipation, helping maximize the battery life of portables.

Click here to download the whitepaper