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DDR3 System On-and-Around the Chip

We saw the other day that Cadence was being aggressive with the memory controller IP from their Denali side. They’re actually trying to create a wider-scoped solution by providing a PCB package that ties in well with their DDR3 memory controller IP.

DDR memory timing is simply nuts, and board layout is critical. Everything matters. So the DDR3 Design-in kit contains the memory controller I/O and IC package model, timing/duration model, connector model, memory model, DIMM topology, and electrical constraints for the controller … Read More → "DDR3 System On-and-Around the Chip"

Vertical or Horizontal?

Once upon a time, Silicon Valley was all about the technology. You developed a skill at something and then applied it to anything that would give you an edge over someone else.

So, for instance, if you’re a company like Wolfson, with a knack for developing analog front-ends for consumer items, then you might do a wide range of them for things like, oh, imaging, audio, etc.

They call that “horizontal” marketing.

But that fell out of favor. Maybe engineers got too busy. Maybe someone had a marketing book … Read More → "Vertical or Horizontal?"

Selling What?

Reading Jim Turley’s article about business models got me thinking about FPGA and EDA companies.  

Yeah, I know. What’s new?

We’ve talked a lot about how EDA companies struggle to find a business model that earns them their fair share of the loot that comes from electronics.  The full-fledged, modern EDA industry has been around for about three decades and… they still drive a huge portion of the technology while reaping a tiny fraction of the rewards.

The fundamental reason for this, I believe, is that they’ … Read More → "Selling What?"

An Alliance of Alliance Members

The other day Mixel announced a MIPI Alliance ecosystem partnership. So… is that a branch of the MIPI Alliance? A new MIPI Alliance? I was a bit confused. (Not an infrequent state of mind for me, but never mind…)

This gets to some of the subtleties of industry partnerships. If you’re not careful, you can run afoul of anti-trust collusion laws. These laws were put in place because, in the olden days, big companies would get together and divide up territories and agree on pricing and basically guarantee that they would all get … Read More → "An Alliance of Alliance Members"

A Simple Brown Paper Bag

Yesterday I went to Mentor’s U2U user event. Something was missing – and it was a good thing.

We editors probably go to more events than your average engineer, but even an engineer that goes to a couple per year  must end up with a basement full of black ballistic nylon bags of various shapes and sizes with logos that ensure that his or her kids will never want to be seen in public with them. We may like the technology behind the logos, but they’re not considered “cool brands.& … Read More → "A Simple Brown Paper Bag"

In a Different Field

Part of the Cadence Allegro release features a new field solver they’ve included for power delivery network (PDN) analysis, the product of collaboration with the University of Illinois, Urbana-Champaign. It’s actually integrated with the PCB editor so that analysis and re-editing can be done without having to swap tools.

We covered field solver technology some time ago, but the target applications we focused on there were for on-chip parasitic extraction or package/chip interactions. … Read More → "In a Different Field"

New PCB Design Mix ‘n’ Match

Yesterday Cadence announced a major update to their Allegro PCB design suite. This is the full-featured set of tools targeted at enterprise (= deep pockets) customers. They found that their offering had outgrown the “good/better/best” grading that had been in place for a long time.

What they’ve done instead is to put in place a baseline tool, Allegro PCB Designer, into which various optional modules can be inserted. These modules provide various higher-value functions, and the licenses can be purchased in quantities different from those purchased for the base product. For example, … Read More → "New PCB Design Mix ‘n’ Match"

Going Up

It’s always helpful when complex new technological ideas can be related to everyday concepts. So when I heard about “test elevators,” proposed by imec, for 3D IC DFT, naturally my interest was piqued. It’s an intriguing image, conjuring up thoughts of complex ways of managing tests on multiple dice.

Alas, as it turns out, there’s really no new technology associated with this: it’s simply the idea of allocating some TSVs for testing. Which … Read More → "Going Up"

FLASH Gets Even Smaller

It feels, at first blush, like the conventional wisdom about floating gate cells not having a future at tiny dimensions may have to go the way lots of conventional wisdom goes. On the heels of Kilopass’s 40-nm MTP announcement, Micron and Intel announced NAND FLASH at as low as 20 nm.

So much for not scalable below 90 nm.

The issue here is too much tunneling when the oxides get too thin. It wasn’t supposed to work with oxides … Read More → "FLASH Gets Even Smaller"

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