Design for portability is a valuable technique for engineers targeting consumer markets, seeking a cost-effective transition from an FPGA platform used for rapid development and prototyping to create price-competitive products that will win sales in fast paced consumer market.

Design Conversion for Marketing Objectives

FPGAs (field programmable gate arrays) provide a powerful tool for designers seeking to satisfy consumer demands for complex, multi-functional products. The FPGA’s fast development cycles accelerate the learning and debugging processes, which serves demands for short time-to-market that is characteristic of the consumer space. Initial … Read More → "Low-Cost ASIC Conversion Targets Consumer Success"

With the usual next-node battle cry of “power, performance, price, and productivity,” Altera sailed into sixty-five-nanometer territory today with the announcement of their much-anticipated Stratix III 65nm high-performance FPGA family. 

Altera has put considerable focus on power with this family, bringing in power-targeted architectural changes paired with powerful design tool support.  For years, power in FPGAs was not an important consideration.  The people paying the big bucks for older-generation FPGAs had power to burn along with their cash.  As times and technologies have changed, however, so has the power picture.  Millions of … Read More → "Stratix III"

The wild wind whistles strange through the bright gloom of eternal daylight in the tightly-sealed semiconductor fab.  In the power-assured place where progress never pauses – where cryptically-coded wafers plod persistently through mysterious machines in the acrid vacuum of the clean room – where white-suited phantoms pass FPGAs through evil rays and deadly potions and spinning saws… something is amiss.

In the nooks and crannies of nanometer features – in the spaces between the spaces – in the places where the design rule checkers never checked, engineers never engineered, and vectors never ventured, there is … Read More → "The Haunting of Fab 51"

A moment later, it was gone. The mark – their goal for their next leg of the race – had unceremoniously sunk into the sea, leaving no trace of its previous location. Spinning on his heels, the tactician saw that the previous mark had also disappeared into the deep green water. The entire race course had effectively suddenly vanished. He looked at his skipper and the other members of their yacht’s “brain trust” in confusion.

The entire racing fleet was now adrift at top speed. In a matter of seconds, what had been a tightly … Read More → "Adrift…"

At first, high speed serial I/O was a checkbox item in FPGAs – either you had it or you didn’t. FPGA vendors bolted transceivers onto their devices, fired off some press releases, and let the games begin. As the race heated up, the competition became one of speed and versatility. FPGA transceiver complexity exploded as vendors vied to lay claim to the most standards and protocols supported, the highest bit rates, the lowest jitter, the highest jitter tolerance, and just about any other specification where a superlative could be claimed.

Of course, the more you … Read More → "Sensible SerDes at Sixty Five"