The contest begins. On the left side of the hall (the “blue” corner), the FPGA design team iterates through the design loop with their high-performance design tools, looking for the optimal placement to reach timing closure. As paths are probed and placements are optimized, it becomes apparent that the problem is the pin assignment. After swapping a few I/O constraints around and re-running place-and-route, the design clears timing analysis with flying colors. Positive slack for all!

On the right side of the hall (the “red” corner), this is all bad news. The … Read More → "Board Room"

Increased gate counts and higher clock speeds in programmable logic ICs have resulted in higher current requirements while smaller device geometries are driving lower core supply voltages. Simultaneously, new communications and memory technologies (DDR, DDR2) are requiring additional new supply voltages. Table 1 shows this low voltage trend in the generational progression of Xilinx FPGAs (Field Programmable Gate Arrays).

Table 1. Voltage Requirements of Xilinx FPGA Families

Cyrus Tsui doesn’t believe in the “Flanking Attack.” He likes the head-on confrontation, even with an entrenched opponent. He’s not intimidated by numbers or humbled by setbacks. He is a true competitor, and has been in the industry long enough to know that the rules of the game change regularly. This month, Lattice Semiconductor, where Cyrus has been CEO for over 15 years, made its most significant strategic announcement in years, challenging industry leaders head-on in what promises to be one of the most aggressive and lucrative battles of the decade for … Read More → "Cyrus Tsui"

Introduction

The applications of Digital Signal Processing (DSP) continue to expand, driven by trends such as the increased use of video and still images and the demand for increasingly reconfigurable systems such as Software Defined Radio (SDR). Many of these applications combine the need for significant DSP processing with cost sensitivity, creating demand for high-performance, low-cost DSP solutions.

General-purpose DSP chips and FPGAs are two common methods of implementing DSP functions, although, until now, the choice of an FPGA implementation has been limited to … Read More → "DSP for Less"

Pay attention now, there will be a quiz.

In today’s lesson, we’re going to pick the best FPGA. Well, more accurately, we’re going to learn how to pick the best FPGA. The actual proof will be left as an exercise for the student. Since we’re engineers, we can’t rely on any touchy-feely stuff. It doesn’t matter who has the coolest name. We don’t even care who’s got the slickest icon printed on top of their BGA packages. We need a formula. … Read More → "Terminology Tango 101"

Imagine watching a professional sports contest (let’s say a basketball game), starting sometime in the middle. In this particular game, there is no visible scoreboard. You watch one team score, then the other. Each seems to be making progress and amassing points, but without a scorecard, you really have no way to tell who’s winning or losing.

There were two exciting announcements in the emerging low-cost, high-volume FPGA market this week. The key issue in this contest is, of course, price. Unfortunately, amidst the flurry of features, claims and specifications, price is the … Read More → "Low Cost Leapfrog"

I always believed that I was interested in electronics as a kid. I now see that I was wrong. After chatting with Ken McElvain at this year’s DAC, I learned that I was merely a poser, dabbling in the discovery of technology. Ken McElvain was interested in electronics. While I sat in my room with my Radio Shack 100-in-1 kit hooking up the multi-colored wires to the spring-loaded terminals, carefully constructing every pre-made project in the book, Ken McElvain was in the backyard with his dad, blowtorching TTL components off discarded circuit boards to stuff into wire-wrap … Read More → "Ken McElvain"

FPGAs are a great solution for prototyping because they offer designers the flexibility to test a design in the application without incurring large NRE charges. Design iterations can be performed using the same FPGA prototype device until the final working solution is attained. However, a completed design often requires a different set of priorities: lower cost, lower power and better performance. Structured ASICs offer a solution to this shift from a prototype emphasis to production design requirements at less risk than a comparable cell-based ASIC implementation. Structured ASICs also offer several key performance advantages over FPGAs, primarily in the … Read More → "Prototype to Production"

All the FPGA action these days is in the new, emerging markets right? As we’ve all discussed for awhile, CPLDs are a nice steady market with slow growth, and networking apps (the ones that built the FPGA industry to where it is today) took a nose-dive a few years back and are out of favor.

According to the world’s largest programmable logic company, this line of reasoning is a bit short-sighted. While Xilinx agrees that there are new and exciting emerging markets out there, they are pointing out, with two announcements this week, … Read More → "Xilinx Goes Retro"

It stands to reason.

Some components of system-on-chip design are static. You’re not going back and re-engineering them every two weeks. The multiplier was designed long ago and doesn’t really need to be designed again every time the moon changes phase. Neither does the PCI core, for that matter. They’re both stable and well-debugged. It’s unlikely that you’re ever going to need to modify or reconfigure them.

Why, then, does it make sense for these common functions to be built out of programmable logic, subject … Read More → "Semi-Programmable"