Computing architectures have reached a critical juncture. The monolithic microprocessor has collided with the thermal wall with a resounding, “Ouch! That’s too hot!” Traditional processor architects have moved on to dual-and-more core processors, pursuing some parallelism to mitigate their power problems. Other technologies have responded with “Hey, if parallelism is the solution, why not really go for it?” Compute acceleration with devices like FPGAs can boost the number of numbers crunched per second per Watt by orders of magnitude, but programming them is an activity akin to custom hardware design – … Read More → "Power Parallelism"

In the good old days, people knew what a LUT was.

Why, when I was a design engineer, we taped out our design on glass – with real tape. There was none of this fancy new lithography. After FPGAs came out, we used to work out the LUT truth tables by hand, coding up Karnaugh maps to minimize our equations, doing De Morgan equivalents… Heck, kids these days with all their fancy IP blocks and algorithm compilers – they couldn’t cross-couple a NAND gate if their life depended on it. Spoiled, I tell … Read More → "Making the MOST"

Three years and over one-hundred-fifty editions ago, the first copy of FPGA Journal rolled off the virtual presses, coursing its way through the digital jungle to about a thousand unsuspecting initial subscribers. Our first feature article, “Making the Transition – FPGA Primer for ASIC Designers,” was well received, as were most of the ninety-one features and hundreds of news stories we ran that first year in 2003 and 2004. If you’ve never browsed our [Read More → "It’s All About Us"

It happens from time to time. Some well-meaning high-tech company notices that they’ve got some pretty cool design tool technology and says to themselves, “Hey, we’ve got some cool design tool technology. Let’s jump into the EDA market!” These are fateful thoughts, however – best pushed aside. In practical terms, they are akin to “Hey, I’ve got myself a pretty cool racing bike – I think I’ll compete in the Tour de France!” Sometimes, though, a company that, perhaps, developed some nice tools for their own internal use, feels just too tempted and takes that … Read More → "Connecting the Camps"

FPGAs fall into two distinct camps – high-performance and low-cost. For several years, the rules and conventions of these strata have been established and followed by FPGA companies. Low-cost or value-based FPGAs are designed with cost as the first priority. Every spare feature is thrown overboard in order to minimize die size and production cost, leading to the lowest possible price-per-LUT for a given amount of programmable fabric. High-end FPGAs, on the other hand, spare no expense in offering the maximum performance and the richest feature sets.

The silicon selection rules for FPGA designers have been, therefore, … Read More → "Lattice Breaks the Rules"