feature article
Subscribe Now

Package Deal

How to Pick the Best Wrapper for Your FPGA

Choosing an FPGA package is both simple and fun.

We have flat-pack, via-stack, timing sometimes outa’ whack; BGA, pin-array, tin-whisker sneak attack, lead-free, QFP, 12-layer PCB; cavity-up, cavity-down, ceramic, plastic, heat-sink ground; flip-chip, classic DIP, moisture-sensitive micro-chip… OK, wait. Let’s break this down.

Package selection is one of the most important and least understood aspects of part selection for most FPGA designers. While the digitally inclined among us are savvy to the subtleties of speed-grade selection and cognizant of the complexities of LUT-counting, we tend to glaze over at mere mention of solder-balls and thermal resistance. In that no man’s land where logic design meets the physical world, our happy realm of zeros and ones is invaded by terrifying creatures like materials properties, mechanical specifications, and ambient temperatures.

You can simplify the problem significantly if you take two important steps. First, partner with the people doing the mechanical and board layout on your project. You’ll find them quite friendly, and they probably paid attention in those classes you avoided, skipped, or slept through in engineering school. The choice of package can have an enormous impact on the cost and complexity of their job as well as on the performance and reliability of your finished project, so it pays to have them heavily involved from the beginning.

Second, you need to make a list of the primary considerations in package selection and decide which ones are priorities for your design. You can use this as a road map when you’re navigating the jargon-laden jungle of package data sheets. When you break down your basic requirements, choosing the package becomes almost an exercise in the obvious.

First up on the list is performance. If your design won’t run at speed and get the data onto and off of the chip at the specified rates, the other criteria will suddenly seem less important. If you are using high-speed I/O or have long signal traces on your board, the package performance can have a significant impact on overall timing. Unfortunately, the package sits right on the seam connecting the world of on-chip timing analysis and the realm of board-based timing. Several vendors are now touting timing solutions that take this critical interface into account. If your design is timing-critical, take the time to make sure this problem is solved first.

Second in our lineup is reliability. If your device will be sitting in a vibration-free chassis at sea level and nobody’s life depends on its 100% functionality, you can probably skip this section. If, on the other hand, your part is to be mounted on a board that will dive into an oil well, be shot into space, run atop a race-car engine, or (to reflect on a recent example) be spinning at 700RPM inside a fighting robot, you need to think about the mechanical reliability of the package and the bonding method, the stability of the package as mounted on a board, and the strength, flexibility, moisture-resistance, radiation-tolerance, and vibration sensitivity of the whole system.

Third up are thermal considerations. FPGAs are known to be somewhat power-hungry compared with many of the devices on your board. All that power generates heat, and heat can mean trouble. Depending on how hot you expect your device to run, you may need a ceramic or thermally enhanced package to keep the blue smoke at bay. In some applications, you’ll need to think about heat sinks, fans, and enclosure modifications to maintain moderate operating temperatures.

Fourth is the environment. If you get past the first three and conclude that you can actually develop a system that will work at speed without falling apart or melting, you want to be sure that you won’t be poisoning the planet with toxic substances left in landfills where they do not belong. While semiconductors and their packaging are far from the worst environmental offenders, there has been significant industry initiative in eliminating heavy metals and other dangerous ingredients in our mass-produced masterpieces of technology. Most FPGA vendors today offer green packaging options, and many customers are starting to require them. Japanese manufacturers, in particular, have taken the lead in demanding lead-free packaging as well as certifying semiconductor suppliers that meet stringent environmental standards with their products.

Fifth, and finally, is cost. While cost is unaccustomed to running last in the race, there is good reason to make it your final and lowest priority consideration in package selection. If you go to the cost option too early, you may find yourself far down the design path with a system that will not work properly or reliably. When thinking about cost, it also pays to go beyond the pins and consider the system-wide cost implications of your package choice. The cheapest package might not necessarily make the lowest total cost solution if it requires more layers of circuit board or more sophisticated manufacturing equipment, or more aggressive cooling. Now that FPGA part costs have plummeted, the packaging as a percentage of total part cost has increased dramatically too, so cost should be a significant (even if comparatively minor) consideration.

Luckily, unlike many engineering decisions, there is no complex trade-off required to balance these options and choose the optimal package for your design. Recently, quad flat no-lead (QFN) packages have gained popularity due to their outstanding performance in most of our listed categories. Also known as micro lead frame (MLF) packages, QFN packages offer improved performance, higher reliability, lower cost, and easier production than ball grid array (BGA) and fine line ball grid array (FBGA) package options, or laminate-based chip-scale packages (CSP).

QFN packages offer small footprints, low overall mounted height, easier mounting with less-expensive equipment, excellent thermal characteristics, and higher density than leadframe packages. Unfortunately, if you have a lot of pins, a QFN package is probably not available for your application. In that case, you’ll most likely be choosing one of the many flavors of BGA packages. Every FPGA vendor offers comprehensive data sheets on their website with details on the manufacturing considerations, performance, and reliability of their packaging options.

For special applications such as high-reliability or hostile environments, you may need to think about ceramic or hermetic specialty packaging. While these tend to be much higher in cost than other packaging options, they are mandatory in many applications. Because of their emphasis on military and aerospace applications, vendors like Aeroflex, Actel and others carry more of these specialized package types than typical FPGA vendors. Their packaging options are perhaps the most diverse in the FPGA industry, even including bare-die options for die-hard do-it-yourselfers.

Keeping your priorities in mind is key for package selection. If you exercise engineering discipline you can make short work of your packaging paradox. With a little cooperation from your newfound friends in physical design, you’ll be able to quickly get back to the fun business of VHDL coding, IP integration and I/O assignment, confident that you picked the proper package for your programmable part.

Leave a Reply

featured blogs
Jun 6, 2023
Learn about our PVT Monitor IP, a key component of our SLM chip monitoring solutions, which successfully taped out on TSMC's N5 and N3E processes. The post Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes appeared first on New Horizons for Chip Design....
Jun 6, 2023
At this year's DesignCon, Meta held a session on '˜PowerTree-Based PDN Analysis, Correlation, and Signoff for MR/AR Systems.' Presented by Kundan Chand and Grace Yu from Meta, they talked about power integrity (PI) analysis using Sigrity Aurora and Power Integrity tools such...
Jun 2, 2023
I just heard something that really gave me pause for thought -- the fact that everyone experiences two forms of death (given a choice, I'd rather not experience even one)....

featured video

The Role of Artificial Intelligence and Machine Learning in Electronic Design

Sponsored by Cadence Design Systems

In this video, we talk to Paul Cunningham, Senior VP and GM at Cadence, about the transformative role of artificial intelligence and machine learning (AI/ML) in electronic designs. We discuss the transformative period we are experiencing with AI and ML and how Cadence is revolutionizing how we design and verify chips through “computationalizing intuition” and building intuitive systems that learn and adapt to the world around them. With human lives at stake, reliability, and safety are paramount.

Learn More

featured paper

EC Solver Tech Brief

Sponsored by Cadence Design Systems

The Cadence® Celsius™ EC Solver supports electronics system designers in managing the most challenging thermal/electronic cooling problems quickly and accurately. By utilizing a powerful computational engine and meshing technology, designers can model and analyze the fluid flow and heat transfer of even the most complex electronic system and ensure the electronic cooling system is reliable.

Click to read more

featured chalk talk

Chipageddon: What's Happening, Why It's Happening and When Will It End
Sponsored by Mouser Electronics and Digi
Semiconductors are an integral part of our design lives, but supply chain issues continue to upset our design processes. In this episode of Chalk Talk, Ronald Singh from Digi and Amelia Dalton investigate the variety of reasons behind today’s semiconductor supply chain woes. They also take a closer look at how a system-on-module approach could help alleviate some of these issues and how you can navigate these challenges for your next design.
Jul 13, 2022
38,813 views