There has been significant research to support the potential performance gains available through the use of reconfigurable hardware for certain classes of computationally-intensive tasks. However, despite well-known advantages, the technology has historically struggled to gain a strong foothold in the high-performance computing (HPC) marketplace. While there were many reasons for this lack of early widespread acceptance, one major issue has been a lack of standards surrounding reconfigurable processors and the absence of a standardized system architecture that can effectively employ them.

Many of the technological barriers to widespread use of reconfigurable computers have been overcome, and with … Read More → "Reconfigurable Computing for Acceleration in HPC"

It was a demonstration that buzzed around the (admittedly small incestuous) industry. A digital clock being powered by a grapefruit. It’s the kind of thing you might see on the Discovery Channel these days, but back in the day, Phillips/Signetics created a local stir with their comparatively ultra-low-power CPLDs. At that time, it was competing with the incumbent PALs that drew about 180 mA of current (and competing with their half- and quarter-power versions made possible by CMOS encroaching on an erstwhile bipolar domain). As the smaller devices became commoditized, the spotlight moved to FPGAs, … Read More → "Making FPGAs Cool Again – Part 1"

Introduction

Since its introduction in 2005, SystemVerilog has been touted as the way to marry design and verification into a single language, enabling design with verification. Despite its blending of the best of Verilog, assertion languages and VHDL, SystemVerilog adoption has been slow — as with any new HDL or design methodology. But the language’s popularity is growing as tool support has improved, starting first with verification teams then expanding to ASIC designers and now also FPGA designers.

Why SystemVerilog in the First Place?

In times … Read More → "SystemVerilog is Coming to FPGA Design"

OK, we have to come clean right away.  In introducing their new 99 cent FPGAs (yep, not a typo), Actel never claimed that they were zero dollars or zero power.  FPGA Journal is adding that part via a superpower we call “editorial license.”  Here’s how it works – some of Actel’s competitors have already called their competing parts “Zero Power” because they have a static power consumption of less than a milliwatt. Apparently, the old ammeters would just show zero when the current dropped into the microamps, and some … Read More → "Zero Power for Zero Dollars"