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Think You Know Where Structured ASICs Belong?

Over the past couple of years, the notion of Structured ASIC and Platform ASIC architectures, let’s refer to both as Structured ASICs, have received a lot of attention from the chip industry. Structured ASIC proponents tout the concept as a way of getting near-ASIC performance and unit pricing without the high NREs and long and complex design cycles of ASICs. On the other side, skeptics dismiss Structured ASICs as a ploy to save what they consider to be a dying ASIC design industry. In reality, the benefits of Structured ASICs lies somewhere between these two viewpoints – exactly … Read More → "Think You Know Where Structured ASICs Belong?"

SDR Prêt-à-Porter

Just three weeks ago, Xilinx announced the latest version of their PlanAhead software, asserting among other things that they had simplified the daunting task of partial reconfiguration. We listened, and went so far as to include a section on this potentially ground breaking technology in our February 7 article on the subject (see article). We acknowledged our hesitation to get too excited about the idea, feeling that it would take a very brave soul indeed to jump in and give it a try. At the time, it felt like the equivalent of … Read More → "SDR Prêt-à-Porter"

How Soft?

If I use the term “software,” a variety of images might appear in the engineering audience’s mind. A software engineer might think of source code in his or her favorite programming language. A hardware engineer might think of a series of instructions to be executed on a Von Neumann architecture. A system designer might visualize a set of capabilities that are easy to modify in the field.

In high-tech, however, definitions are not well behaved. Things just refuse to stay in their boxes. Over time, inertia builds around a label or concept, only to be upset … Read More → "How Soft?"

How to Avoid PCB Libraries Stifling FPGA Design

FPGA and PCB design teams have begun to leverage the flexibility of FPGA devices to create complex systems while optimizing their PCB design for performance as well as manufacturing costs. The immediate pay-off is a substantial decrease in design cycle time, from weeks to minutes while at the same time eliminating design risks associated with late design changes. The business critical benefit is pure cost savings derived from optimizing the PCB manufacturing process. There are a number of PCB manufacturing optimizations possible as a result of tuning the FPGA/PCB interfaces:

 

< … Read More → "How to Avoid PCB Libraries Stifling FPGA Design"

Upping the Low-Cost Ante

In the good old days, there was just one kind of FPGA – the “big” kind. Big is in quotes, of course, because even today’s most modest, miserly devices are bigger and faster than the best we could muster a decade ago. However, as the high end of FPGA technology rode the rocket of Moore’s Law toward the sky, becoming a viable solution for more and more complex applications, a new creature was born – the low-cost FPGA.

The concept seemed simple enough – “normal” high-end FPGAs were optimized for performance. Nothing was held back … Read More → "Upping the Low-Cost Ante"

Lattice Joins the Fray

The elite party of 90nm high-performance FPGA suppliers has just been crashed. The two big burly guards at the entrance to the VIP room were evidently not paying attention, because Lattice Semiconductor just waltzed right in – as if anybody that wanted to could whip up an FPGA family with 3.4Gbps SerDes transceivers, 2Gbps parallel I/O, up to 115K LUTs, loads of hard IP, and up to 500MHz fabric performance. Did nobody notice those 300mm wafers in their pockets?

For about a year now, only Xilinx and Altera have claimed turf in the 90nm FPGA arena. … Read More → "Lattice Joins the Fray"

MIPS Goes Multithreaded

Although most designers don’t often consider it, there are different formulas for best overall system performance from embedded and stand-alone processors, too. Even though there’s no governing league making and changing the racing regulations, parameters like total system cost, power consumption, memory bandwidth, silicon area, and process profile rule the day when choosing a processor for your system design. The tradeoffs that make the best mix of performance on standalone processors can be completely different than those that give the best results in an embedded processor core.

When MIPS designed their new 34K … Read More → "MIPS Goes Multithreaded"

Reconfigurable Computing in Real-World Applications

Developers have long been intrigued by the potential of reconfigurable computing (RC) to accelerate some computationally-intensive high-performance computing (HPC) applications. But the barriers to achieving the order-of-magnitude performance gains RC can theoretically provide are well known: the complexity of programming for RC devices and the limitations of the hardware and software traditionally used to support them. As a result, software developers have focused on fine tuning applications to run faster on standard microprocessors, and have achieved important percentage gains.

Now, emerging systems like the Cray XD1 are bringing RC application acceleration into the … Read More → "Reconfigurable Computing in Real-World Applications"

Planning Ahead

It’s a cold February morning in a well-hidden corner of Silicon Valley. The air is perfectly still. The sun is just rising above the hills, although it isn’t clearly visible through the dissipating ground fog cast over the region by the bay. There is a light frost on the grass, even though the temperature has been in the 40s all night. That’s one of the big issues with fictional, metaphoric introductions to technical articles – continuity problems. These things clearly would never stand up to an engineering design review.

Read More → "Planning Ahead"

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