Content and concept are an interesting combination. People read FPGA and Structured ASIC Journal each week to learn from its content – articles, announcements, analysis, advertisements, and alliteration — all of them working together to inform and entertain engineers interested in programmable logic and structured ASIC design. Interestingly, it turns out that there’s a lot we can learn about programmable logic from FPGA Journal’s concept, too. That’s because FPGA Journal is to technical publications what FPGAs are to system design – highly flexible, fast to market, field programmable, field upgradeable, and at … Read More → "Field Programmable Journalism"

Geologic time is difficult for humans to visualize. Great continents slamming into each other with epic force, reshaping the earth’s surface, don’t seem so impressive when the movement is slowed down to an almost imperceptible rate. The only time we notice the effect is when transients like earthquakes, tsunamis and volcanic eruptions hint at the unwavering determination of the underlying forces. As electronic designers, however, we have some facility in dealing with alternate orders of magnitude in the time scale. We understand that nanoseconds and milliseconds are worlds apart, even though, as humans, we can& … Read More → "Tale of the Tools"

In the rough-and-tumble, day-to-day, my-chip’s-bigger-than-your-chip schoolyard scrap that characterizes the top tier of the FPGA industry, a glimpse of vision, long-term insight and strategy are a rare breath of fresh air. We often feel that the two toughest competitors in the business spend too much time staring each other down and not enough time strategizing on how to conquer more of the vast landscape of logic design opportunity waiting patiently at the forefronts of their fiefdoms. However, when we sat down this week with Danny Biran, Altera’s Vice President of Product and Corporate Marketing, vision … Read More → "Altera Looks Forward"

Every year, FPGA and Structured ASIC Journal has conducted a survey of design teams that have recently completed projects using FPGAs. We collect and analyze a large volume of responses from readers regarding their completed projects, and we publish and sell a detailed report to companies that have a vested interest in gathering data about the current behaviors of FPGA design teams. This is nothing unusual, as many media companies perform similar research and offer similar studies to their customers. This time, however, we noticed one thing that was unusual. There seems to be a shift that … Read More → "Bundling Performance"

In a traditional FPGA design flow, crafting the hardware architecture and writing VHDL or Verilog for RTL synthesis requires considerable effort. The code must follow a synthesis standard, meet timing, implement the interface specification, and function correctly. Given enough time, a design team is capable of meeting all these constraints. However, time is one thing that is always in short supply. Deadlines imposed by time to market pressures often force designers to compromise, resulting in them to settle for ‘good enough’ by re-using blocks and IP that are over designed for their application.

In the … Read More → "Just What is Algorithmic Synthesis?"

Price, Performance, and Power – the three Ps of Moore’s Law — have fueled four decades of technological fury. Each new process node brought us more gates per square meter of silicon, reducing price. Each shrink of the gate also brought us faster toggle rates, giving higher performance, and each narrowing also gave us the opportunity to operate at lower supply voltages, giving less dynamic power consumption. It seemed as if everything would improve exponentially forever.

Of course, nothing is free. There has always been another exponential curve at work as well – that … Read More → "More and Moore"