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Status Quopia

Structured ASIC Captures Mindshare

“You don’t understand,” my father patiently explained. “People have enormous collections of vinyl records. They’re never going to switch to a new format like compact disc, even if the sound and convenience are better. There’s just too much already invested.” Generally, Dad was a progressive, technically-savvy, keep-up-with-change kinda’ guy. On some issues, however, he just couldn’t see past the status-quo. His experience had built a level of technology-rooted myopia that his vision couldn’t overcome. When the new thing came along, even though its technical merits were compelling, he couldn’t imagine the cultural change that would cause it to catch on.

Structured ASIC has been that shiny, new technology on the block for a couple of years now. While everybody acknowledged that the approach had compelling technical and economic advantages, most people just couldn’t visualize its assimilation into mainstream system design. The more traditional approaches like FPGA, ASSP, Standard Cell, and fabless-COT had too much mental inertia.

Today, however, that mindset is starting to change. Structured ASIC companies are seeing a strong increase in sockets, and the new methodology is gradually weaving itself into the fabric of system design. People tend to view structured (or platform) ASIC from the perspective they already know. FPGA designers see structured ASICs as big, fast, low-power, non-reprogrammable FPGAs. Cell-based ASIC designers view them as smaller, low-NRE ASICs.

We took a closer look at three structured ASIC companies to see what kinds of customers they’re wooing and what kinds of sockets they’re winning. Each vendor brings a different perspective and different strengths to the party, with the result that they are each winning a different segment of the market. Interestingly, none of the vendors reports seeing the others often in competitive situations. Usually, they find themselves competing with some alternative (non-structured ASIC) technology.

ChipX has a long history in structured ASIC-style design. The company has concentrated its structured-ASIC efforts in focusing on vertical markets where the value of structured ASIC’s unique features is high. “People want to keep costs and development times down,” explains Elie Massabki, vice president of marketing at ChipX. “We can provide solutions for many high-speed and low-power problems with much lower risk and lower NRE than with traditional ASICs.” ChipX has emphasized high-speed connectivity standards pre-designed, so you can drop them into your system more quickly and with lower risk than designing them yourself. ChipX markets their solution as a “SideChip” in combination with a standard-cell ASIC to provide an easy-to-change integration conduit for rapidly evolving and diverse standards.

Compared with standard-cell ASICs, structured ASICs have a much lower non-recurring engineering (NRE) cost – often 10% or less of the NRE of a traditional ASIC. Design cycles are much shorter too. Since most of the hard-core design for manufacturing and layout-level verification has been done in advance, the design cycle is shorter and simpler, with lower risk. All this is good news for system designers trying to hit narrow market windows with short design cycles.

Compared with FPGAs, structured ASICs fly over the top, delivering higher performance and higher density with lower power consumption and lower unit cost than FPGAs can muster. By leaving programmability on the table, structured ASICs gain about a 10X advantage in logic fabric efficiency – both in density and power consumption, over FPGAs. This means that the typical low-end structured ASIC application is probably too big for any but the largest FPGAs, and then you’re comparing the Godiva end of the FPGA spectrum with the jelly-bean side of structured ASIC.

Typically, structured ASIC customers fall into one of two categories. Either they are moving up from a design that was implemented in FPGAs, looking for higher performance, lower cost, and lower power consumption, or they’re trying to do ASIC-on-the-cheap, taking advantage of the shorter design cycles and lower NRE of structured ASIC to get a product to market faster and at lower total cost.

Two structured-ASIC suppliers bolster their lines with smooth transitions to or from other implementation technologies. In each case, the transition is from an initial “let’s get to market fast” implementation to a higher-volume, lower cost option when your product hits the high-volume home run. In one case, structured ASIC is the starting point, and in the other, the destination.

LSI Logic’s RapidChip family has gained fast traction in structured ASIC. It’s a good thing, too. Talk on the street said that LSI practically bet the company on RapidChip when they began the effort a few years ago. Even if that was somewhat of an exaggeration, it is obvious that the program is strategically very important to LSI logic, and the company has put considerable weight behind driving RapidChip to its success. “We have a vertical market across five areas: military and aerospace, industrial and office automation, communications, consumer, and storage,” says Robert Bielby, vice president of LSI Logic’s custom solutions group. “We have seen design wins with RapidChip across all these markets and in all geographies.”

Bielby explains that structured/platform ASIC (LSI calls RapidChip a “platform” ASIC) represents a unique total-cost-of-ownership value proposition. “Unit volumes for RapidChip customers are such that standard cell would be impractical because of the initial development cost,” Bielby continues. “If they find themselves at a higher volume later, we can help them transition smoothly to a standard-cell solution to further reduce unit cost.” RapidChip is designed in a wide range of what the company calls “Platform ASIC Slices,” with each slice containing a different mix of gates, memory, and hard-IP. The slices are pre-made and require only 4 layers of metal customization to complete a customer’s particular application. Because the slice is pre-designed and pre-verified, the design and customization time, as well as the risk, are greatly reduced when compared with cell-based alternatives.

Altera’s HardCopy structured ASIC family was initially aimed at the FPGA cost-reduction crowd. As their presence has matured, however, they’ve seen significant business from both FPGA conversion and ground-up structured-ASIC design. The unique value that HardCopy brings to the table is the FPGA-rooted design flow. To design a HardCopy device, you first implement and test your design using Altera’s Stratix or Stratix II FPGAs. You can even go to production using the FPGA version of your product. Once you’ve worked out the bugs and are happy with the FPGA version, Altera will create a HardCopy implementation directly from your FPGA design. You end up with higher performance, lower power consumption, and lower unit cost when you’re ready to take your design to volume.

Altera now sees customers planning their product development and introduction strategies with HardCopy in mind. “We’ve seen customers radically change their approach between their first HardCopy design and their second,” says Ro Chawla, senior manager of HardCopy business development at Altera. “By their second design, they sometimes send FPGA versions of the design to their customers and OEMs for evaluation. This allows the customers/OEMs to tweak the FPGA version of the design, feeding the changes back before a HardCopy version is created. They can then integrate changes from a number of customers back into a single HardCopy version. If one customer needs something unique, they can do a separate HardCopy version just for them.”

It’s not just the silicon that makes structured ASIC attractive. The design flow and tool picture is also much cheaper, simpler, and easier than its standard-cell counterpart. A few companies have jumped on the structured-ASIC train early and are reaping the rewards of being first with a solid solution in a new market. In an effort to diversify their offering, Synplicity made a major commitment to structured-ASIC development several years ago. Today, their tools are in just about every structured-ASIC flow on the market. Developing from their FPGA-based roots, Synplicity has worked to make structured- ASIC tools much easier to use and support than traditional ASIC-design software. They’ve changed the business model as well, often licensing single-vendor versions of the tools through the structured-ASIC company, allowing the customers to buy a complete tool solution directly.

Magma Design Automation has also turned their sights on structured ASIC recently, introducing solutions for several vendors. “For structured-ASIC designs to be successful at 90nm, we see a lot of the same issues as standard-cell ASIC,” says Behrooz Zahiri, director of marketing at Magma. “Signal integrity, timing closure, power – they’re all design problems in structured ASIC as well.”

Because of Magma’s big presence in the customer-owned tooling (COT) processes, they’re starting to see a unique phenomenon in structured ASIC as well. “We see customers interested in creating COT methodologies based on structured-ASIC technology,” continues Zahiri. “They need something to reduce risk and cost at 90nm and 65nm, and a structured-ASIC approach gives them a way to spread verification costs over a number of designs.” COT customers are primarily concerned with shrinking schedules and reducing risk. Creating their own platforms that operate across a number of products and product lines can have a substantial business impact by reeling in development schedules.

Structured ASIC is definitely here to stay, at least until something better comes along. The diversity of approaches and applications just starting to emerge is evidence that the methodology has a wide range of applicability, bringing compelling benefits to a diverse audience. As customer successes become better known, and as vendors’ structured ASIC investments start to generate substantial returns, we’re likely to see only more activity in the area.

It’s OK to hang onto those LPs, though. Something about the sound of a diamond dragging across vinyl will never quite be duplicated by digital technology.

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